diff --git a/mistral/arch.cc b/mistral/arch.cc
index 9dd2e81b..cb2016bd 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -43,7 +43,7 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 #undef X
 }
 
-CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi,
+CycloneV::rnode_coords Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi,
                                    int pi) const
 {
     auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
diff --git a/mistral/arch.h b/mistral/arch.h
index bc950566..d99cefb8 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -466,7 +466,7 @@ struct Arch : BaseArch<ArchRanges>
 
     void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
 
-    CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1,
+    CycloneV::rnode_coords find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1,
                                  int pi = -1) const;
     WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
     bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
diff --git a/mistral/archdefs.h b/mistral/archdefs.h
index f4040398..ca88e3f3 100644
--- a/mistral/archdefs.h
+++ b/mistral/archdefs.h
@@ -88,13 +88,13 @@ struct BelId
     unsigned int hash() const { return mkhash(pos, z); }
 };
 
-static constexpr auto invalid_rnode = std::numeric_limits<CycloneV::rnode_t>::max();
+static constexpr auto invalid_rnode = std::numeric_limits<CycloneV::rnode_coords>::max();
 
 struct WireId
 {
     WireId() = default;
-    explicit WireId(CycloneV::rnode_t node) : node(node){};
-    CycloneV::rnode_t node = invalid_rnode;
+    explicit WireId(CycloneV::rnode_coords node) : node(node){};
+    CycloneV::rnode_coords node = invalid_rnode;
 
     // Wires created by nextpnr have rnode type >= 128
     bool is_nextpnr_created() const
@@ -112,8 +112,8 @@ struct WireId
 struct PipId
 {
     PipId() = default;
-    PipId(CycloneV::rnode_t src, CycloneV::rnode_t dst) : src(src), dst(dst){};
-    CycloneV::rnode_t src = invalid_rnode, dst = invalid_rnode;
+    PipId(CycloneV::rnode_coords src, CycloneV::rnode_coords dst) : src(src), dst(dst){};
+    CycloneV::rnode_coords src = invalid_rnode, dst = invalid_rnode;
 
     bool operator==(const PipId &other) const { return src == other.src && dst == other.dst; }
     bool operator!=(const PipId &other) const { return src != other.src || dst != other.dst; }
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index e3268810..d2d72d8d 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -30,13 +30,13 @@ struct MistralBitgen
     Context *ctx;
     CycloneV *cv;
 
-    using rnode_t = CycloneV::rnode_t;
-    using pnode_t = CycloneV::pnode_t;
+    using rnode_coords = CycloneV::rnode_coords;
+    using pnode_coords = CycloneV::pnode_coords;
     using pos_t = CycloneV::pos_t;
     using block_type_t = CycloneV::block_type_t;
     using port_type_t = CycloneV::port_type_t;
 
-    rnode_t find_rnode(block_type_t bt, pos_t pos, port_type_t port, int bi = -1, int pi = -1) const
+    rnode_coords find_rnode(block_type_t bt, pos_t pos, port_type_t port, int bi = -1, int pi = -1) const
     {
         auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi);
         auto rn1 = cv->pnode_to_rnode(pn1);
diff --git a/mistral/delay.cc b/mistral/delay.cc
index 1ef9be6b..e7c8918b 100644
--- a/mistral/delay.cc
+++ b/mistral/delay.cc
@@ -303,7 +303,7 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
     mistral::AnalogSim::wave input_wave[2], output_wave[2];
     mistral::AnalogSim::time_interval output_delays[2];
     mistral::AnalogSim::time_interval output_delay_sum[2];
-    std::vector<std::pair<mistral::CycloneV::rnode_t, int>> outputs;
+    std::vector<std::pair<mistral::CycloneV::rnode_coords, int>> outputs;
     auto temp = mistral::CycloneV::T_100;
     auto est = mistral::CycloneV::EST_SLOW;
 
@@ -378,13 +378,13 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
                                           : mistral::CycloneV::RF_RISE;
             mistral::AnalogSim sim;
             int input = -1;
-            std::vector<std::pair<mistral::CycloneV::rnode_t, int>> outputs;
+            std::vector<std::pair<mistral::CycloneV::rnode_coords, int>> outputs;
             cyclonev->rnode_timing_build_circuit(src.node, temp, CycloneV::DELAY_MAX, actual_edge, sim, input, outputs);
 
             sim.set_input_wave(input, input_wave[edge]);
             auto o = std::find_if(
                     outputs.begin(), outputs.end(),
-                    [&](std::pair<mistral::CycloneV::rnode_t, int> output) { return output.first == dst.node; });
+                    [&](std::pair<mistral::CycloneV::rnode_coords, int> output) { return output.first == dst.node; });
             NPNR_ASSERT(o != outputs.end());
 
             output_wave[edge].clear();