caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

mistral: update to mistral dc82215

Browse Source
This commit is contained in:
Lofty 2023-09-02 10:12:54 +01:00
parent a9a9251e42
commit 5b99b99859
5 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
mistral/arch.cc
View File

@ -43,7 +43,7 @@ void IdString::initialize_arch(const BaseCtx *ctx)
#undef X #undef X
} }
CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi, CycloneV::rnode_coords Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi,
int pi) const int pi) const
{ {
auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi); auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);

2
mistral/arch.h
View File

@ -466,7 +466,7 @@ struct Arch : BaseArch<ArchRanges>
void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire); void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, CycloneV::rnode_coords find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1,
int pi = -1) const; int pi = -1) const;
WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const; WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const; bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;

10
mistral/archdefs.h
View File

@ -88,13 +88,13 @@ struct BelId
unsigned int hash() const { return mkhash(pos, z); } unsigned int hash() const { return mkhash(pos, z); }
}; };
static constexpr auto invalid_rnode = std::numeric_limits<CycloneV::rnode_t>::max(); static constexpr auto invalid_rnode = std::numeric_limits<CycloneV::rnode_coords>::max();
struct WireId struct WireId
{ {
WireId() = default; WireId() = default;
explicit WireId(CycloneV::rnode_t node) : node(node){}; explicit WireId(CycloneV::rnode_coords node) : node(node){};
CycloneV::rnode_t node = invalid_rnode; CycloneV::rnode_coords node = invalid_rnode;
// Wires created by nextpnr have rnode type >= 128 // Wires created by nextpnr have rnode type >= 128
bool is_nextpnr_created() const bool is_nextpnr_created() const
@ -112,8 +112,8 @@ struct WireId
struct PipId struct PipId
{ {
PipId() = default; PipId() = default;
PipId(CycloneV::rnode_t src, CycloneV::rnode_t dst) : src(src), dst(dst){}; PipId(CycloneV::rnode_coords src, CycloneV::rnode_coords dst) : src(src), dst(dst){};
CycloneV::rnode_t src = invalid_rnode, dst = invalid_rnode; CycloneV::rnode_coords src = invalid_rnode, dst = invalid_rnode;
bool operator==(const PipId &other) const { return src == other.src && dst == other.dst; } bool operator==(const PipId &other) const { return src == other.src && dst == other.dst; }
bool operator!=(const PipId &other) const { return src != other.src || dst != other.dst; } bool operator!=(const PipId &other) const { return src != other.src || dst != other.dst; }

6
mistral/bitstream.cc
View File

@ -30,13 +30,13 @@ struct MistralBitgen
Context *ctx; Context *ctx;
CycloneV *cv; CycloneV *cv;
using rnode_t = CycloneV::rnode_t; using rnode_coords = CycloneV::rnode_coords;
using pnode_t = CycloneV::pnode_t; using pnode_coords = CycloneV::pnode_coords;
using pos_t = CycloneV::pos_t; using pos_t = CycloneV::pos_t;
using block_type_t = CycloneV::block_type_t; using block_type_t = CycloneV::block_type_t;
using port_type_t = CycloneV::port_type_t; using port_type_t = CycloneV::port_type_t;
rnode_t find_rnode(block_type_t bt, pos_t pos, port_type_t port, int bi = -1, int pi = -1) const rnode_coords find_rnode(block_type_t bt, pos_t pos, port_type_t port, int bi = -1, int pi = -1) const
{ {
auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi); auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi);
auto rn1 = cv->pnode_to_rnode(pn1); auto rn1 = cv->pnode_to_rnode(pn1);

6
mistral/delay.cc
View File

@ -303,7 +303,7 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
mistral::AnalogSim::wave input_wave[2], output_wave[2]; mistral::AnalogSim::wave input_wave[2], output_wave[2];
mistral::AnalogSim::time_interval output_delays[2]; mistral::AnalogSim::time_interval output_delays[2];
mistral::AnalogSim::time_interval output_delay_sum[2]; mistral::AnalogSim::time_interval output_delay_sum[2];
std::vector<std::pair<mistral::CycloneV::rnode_t, int>> outputs; std::vector<std::pair<mistral::CycloneV::rnode_coords, int>> outputs;
auto temp = mistral::CycloneV::T_100; auto temp = mistral::CycloneV::T_100;
auto est = mistral::CycloneV::EST_SLOW; auto est = mistral::CycloneV::EST_SLOW;
@ -378,13 +378,13 @@ bool Arch::getArcDelayOverride(const NetInfo *net_info, const PortRef &sink, Del
: mistral::CycloneV::RF_RISE; : mistral::CycloneV::RF_RISE;
mistral::AnalogSim sim; mistral::AnalogSim sim;
int input = -1; int input = -1;
std::vector<std::pair<mistral::CycloneV::rnode_t, int>> outputs; std::vector<std::pair<mistral::CycloneV::rnode_coords, int>> outputs;
cyclonev->rnode_timing_build_circuit(src.node, temp, CycloneV::DELAY_MAX, actual_edge, sim, input, outputs); cyclonev->rnode_timing_build_circuit(src.node, temp, CycloneV::DELAY_MAX, actual_edge, sim, input, outputs);
sim.set_input_wave(input, input_wave[edge]); sim.set_input_wave(input, input_wave[edge]);
auto o = std::find_if( auto o = std::find_if(
outputs.begin(), outputs.end(), outputs.begin(), outputs.end(),
[&](std::pair<mistral::CycloneV::rnode_t, int> output) { return output.first == dst.node; }); [&](std::pair<mistral::CycloneV::rnode_coords, int> output) { return output.first == dst.node; });
NPNR_ASSERT(o != outputs.end()); NPNR_ASSERT(o != outputs.end());
output_wave[edge].clear(); output_wave[edge].clear();