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less horrid way of handling gfx ids

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This commit is contained in:
Miodrag Milanovic 2024-11-20 15:06:51 +01:00
parent 9b667227b5
commit 5c46ab5f7e
7 changed files with 205 additions and 187 deletions
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34
himbaechel/himbaechel_dbgen/chip.py
View File

@ -144,7 +144,7 @@ class TileWireData:
index: int
name: IdString
wire_type: IdString
tile_wire: int
gfx_wire_id: int
const_value: IdString = field(default_factory=list)
flags: int = 0
timing_idx: int = -1
@ -167,7 +167,7 @@ class TileWireData:
def serialise(self, context: str, bba: BBAWriter):
bba.u32(self.name.index)
bba.u32(self.wire_type.index)
bba.u32(self.tile_wire)
bba.u32(self.gfx_wire_id)
bba.u32(self.const_value.index)
bba.u32(self.flags)
bba.u32(self.timing_idx)
@ -232,13 +232,13 @@ class TileType(BBAStruct):
def create_wire(self, name: str, type: str="", const_value: str=""):
# Create a new tile wire of a given name and type (optional) in the tile type
tile_wire = 0
if ("TILE_WIRE_" + name) in self.gfx_wire_ids:
tile_wire = self.gfx_wire_ids["TILE_WIRE_" + name]
gfx_wire_id = 0
if (name) in self.gfx_wire_ids:
gfx_wire_id = self.gfx_wire_ids[name]
wire = TileWireData(index=len(self.wires),
name=self.strs.id(name),
wire_type=self.strs.id(type),
tile_wire=tile_wire,
gfx_wire_id=gfx_wire_id,
const_value=self.strs.id(const_value))
self._wire2idx[wire.name] = wire.index
self.wires.append(wire)
@ -875,17 +875,15 @@ class Chip:
self.serialise(bba)
bba.pop()
def read_gfx_h(self, filename):
def read_gfxids(self, filename):
idx = 1
with open(filename) as f:
state = 0
for line in f:
if state == 0 and line.startswith("enum GfxTileWireId"):
state = 1
elif state == 1 and line.startswith("};"):
state = 0
elif state == 1 and (line.startswith("{") or line.strip() == ""):
pass
elif state == 1:
idx = len(self.gfx_wire_ids)
name = line.strip().rstrip(",")
self.gfx_wire_ids[name] = idx
l = line.strip()
if not l.startswith("X("):
continue
l = l[2:]
assert l.endswith(")"), l
l = l[:-1].strip()
self.gfx_wire_ids[l] = idx
idx += 1

53
himbaechel/himbaechel_gfxids.h Normal file
View File

@ -0,0 +1,53 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 gatecat <gatecat@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef HIMBAECHEL_GFXIDS_H
#define HIMBAECHEL_GFXIDS_H
/*
This enables use of 'gfxids' similar to a 'constids' in a HIMBAECHEL uarch.
To use:
- create a 'gfxids.inc' file in your uarch folder containing one ID per line; inside X( )
- set the HIMBAECHEL_UARCH macro to uarch namespace
- set the HIMBAECHEL_GFXIDS macro to the path to this file relative to the generic arch base
- include this file
*/
#include "nextpnr_namespaces.h"
NEXTPNR_NAMESPACE_BEGIN
namespace HIMBAECHEL_UARCH {
#ifndef Q_MOC_RUN
enum GfxTileWireId
{
GFX_WIRE_NONE
#define X(t) , GFX_WIRE_##t
#include HIMBAECHEL_GFXIDS
#undef X
,
};
#endif
};
NEXTPNR_NAMESPACE_END
using namespace NEXTPNR_NAMESPACE_PREFIX HIMBAECHEL_UARCH;
#endif

2
himbaechel/uarch/example/CMakeLists.txt
View File

@ -22,7 +22,7 @@ foreach(device ${HIMBAECHEL_EXAMPLE_DEVICES})
bbasm
${CMAKE_CURRENT_SOURCE_DIR}/example_arch_gen.py
${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
${CMAKE_CURRENT_SOURCE_DIR}/gfx.h
${CMAKE_CURRENT_SOURCE_DIR}/gfxids.inc
VERBATIM)
list(APPEND chipdb_binaries ${device_bin})
endforeach()

20
himbaechel/uarch/example/example.cc
View File

@ -21,13 +21,15 @@
#include "log.h"
#include "nextpnr.h"
#include "util.h"
#include "gfx.h"
#include "himbaechel_helpers.h"
#define GEN_INIT_CONSTIDS
#define HIMBAECHEL_CONSTIDS "uarch/example/constids.inc"
#define HIMBAECHEL_GFXIDS "uarch/example/gfxids.inc"
#define HIMBAECHEL_UARCH example
#include "himbaechel_constids.h"
#include "himbaechel_gfxids.h"
NEXTPNR_NAMESPACE_BEGIN
@ -189,15 +191,15 @@ struct ExampleImpl : HimbaechelAPI
switch (wire_type.index)
{
case id_LUT_INPUT.index:
z = (tilewire - TILE_WIRE_L0_I0) / 4;
z = (tilewire - GFX_WIRE_L0_I0) / 4;
el.x1 = loc.x + 0.10;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.85 - z * 0.1 - ((tilewire - TILE_WIRE_L0_I0) % 4 + 1) * 0.01;
el.y1 = loc.y + 0.85 - z * 0.1 - ((tilewire - GFX_WIRE_L0_I0) % 4 + 1) * 0.01;
el.y2 = el.y1;
g.push_back(el);
break;
case id_LUT_OUT.index:
z = tilewire - TILE_WIRE_L0_O;
z = tilewire - GFX_WIRE_L0_O;
el.x1 = loc.x + 0.40;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
@ -205,7 +207,7 @@ struct ExampleImpl : HimbaechelAPI
g.push_back(el);
break;
case id_FF_DATA.index:
z = tilewire - TILE_WIRE_L0_D;
z = tilewire - GFX_WIRE_L0_D;
el.x1 = loc.x + 0.50;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
@ -213,7 +215,7 @@ struct ExampleImpl : HimbaechelAPI
g.push_back(el);
break;
case id_FF_OUT.index:
z = tilewire - TILE_WIRE_L0_Q;
z = tilewire - GFX_WIRE_L0_Q;
el.x1 = loc.x + 0.80;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
@ -238,7 +240,7 @@ struct ExampleImpl : HimbaechelAPI
switch (wire_type.index)
{
case id_RAM_IN.index:
z = tilewire - TILE_WIRE_RAM_WA0;
z = tilewire - GFX_WIRE_RAM_WA0;
el.x1 = loc.x + 0.20;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.78 - z * 0.015;
@ -246,7 +248,7 @@ struct ExampleImpl : HimbaechelAPI
g.push_back(el);
break;
case id_RAM_OUT.index:
z = tilewire - TILE_WIRE_RAM_DO0;
z = tilewire - GFX_WIRE_RAM_DO0;
el.x1 = loc.x + 0.75;
el.x2 = el.x1 + 0.05;
el.y1 = loc.y + 0.78 - z * 0.015;
@ -303,7 +305,7 @@ struct ExampleImpl : HimbaechelAPI
el.style = style;
int z;
if (src_type == id_LUT_OUT && dst_type == id_FF_DATA) {
z = src_id - TILE_WIRE_L0_O;
z = src_id - GFX_WIRE_L0_O;
el.x1 = loc.x + 0.45;
el.y1 = loc.y + 0.85 - z * 0.1 - 0.025;
el.x2 = loc.x + 0.50;

2
himbaechel/uarch/example/example_arch_gen.py
View File

@ -237,7 +237,7 @@ def main():
ch = Chip("example", "EX1", X, Y)
# Init constant ids
ch.strs.read_constids(path.join(path.dirname(__file__), "constids.inc"))
ch.read_gfx_h(path.join(path.dirname(__file__), "gfx.h"))
ch.read_gfxids(path.join(path.dirname(__file__), "gfxids.inc"))
logic = create_logic_tiletype(ch)
io = create_io_tiletype(ch)
bram = create_bram_tiletype(ch)

158
himbaechel/uarch/example/gfx.h
View File

@ -1,158 +0,0 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 gatecat <gatecat@ds0.me>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef HIMBAECHEL_EXAMPLE_GFX_H
#define HIMBAECHEL_EXAMPLE_GFX_H
#include "nextpnr.h"
NEXTPNR_NAMESPACE_BEGIN
enum GfxTileWireId
{
TILE_WIRE_NONE,
TILE_WIRE_L0_O,
TILE_WIRE_L1_O,
TILE_WIRE_L2_O,
TILE_WIRE_L3_O,
TILE_WIRE_L4_O,
TILE_WIRE_L5_O,
TILE_WIRE_L6_O,
TILE_WIRE_L7_O,
TILE_WIRE_L0_I0,
TILE_WIRE_L0_I1,
TILE_WIRE_L0_I2,
TILE_WIRE_L0_I3,
TILE_WIRE_L1_I0,
TILE_WIRE_L1_I1,
TILE_WIRE_L1_I2,
TILE_WIRE_L1_I3,
TILE_WIRE_L2_I0,
TILE_WIRE_L2_I1,
TILE_WIRE_L2_I2,
TILE_WIRE_L2_I3,
TILE_WIRE_L3_I0,
TILE_WIRE_L3_I1,
TILE_WIRE_L3_I2,
TILE_WIRE_L3_I3,
TILE_WIRE_L4_I0,
TILE_WIRE_L4_I1,
TILE_WIRE_L4_I2,
TILE_WIRE_L4_I3,
TILE_WIRE_L5_I0,
TILE_WIRE_L5_I1,
TILE_WIRE_L5_I2,
TILE_WIRE_L5_I3,
TILE_WIRE_L6_I0,
TILE_WIRE_L6_I1,
TILE_WIRE_L6_I2,
TILE_WIRE_L6_I3,
TILE_WIRE_L7_I0,
TILE_WIRE_L7_I1,
TILE_WIRE_L7_I2,
TILE_WIRE_L7_I3,
TILE_WIRE_L0_D,
TILE_WIRE_L1_D,
TILE_WIRE_L2_D,
TILE_WIRE_L3_D,
TILE_WIRE_L4_D,
TILE_WIRE_L5_D,
TILE_WIRE_L6_D,
TILE_WIRE_L7_D,
TILE_WIRE_L0_Q,
TILE_WIRE_L1_Q,
TILE_WIRE_L2_Q,
TILE_WIRE_L3_Q,
TILE_WIRE_L4_Q,
TILE_WIRE_L5_Q,
TILE_WIRE_L6_Q,
TILE_WIRE_L7_Q,
TILE_WIRE_RAM_WA0,
TILE_WIRE_RAM_WA1,
TILE_WIRE_RAM_WA2,
TILE_WIRE_RAM_WA3,
TILE_WIRE_RAM_WA4,
TILE_WIRE_RAM_WA5,
TILE_WIRE_RAM_WA6,
TILE_WIRE_RAM_WA7,
TILE_WIRE_RAM_WA8,
TILE_WIRE_RAM_RA0,
TILE_WIRE_RAM_RA1,
TILE_WIRE_RAM_RA2,
TILE_WIRE_RAM_RA3,
TILE_WIRE_RAM_RA4,
TILE_WIRE_RAM_RA5,
TILE_WIRE_RAM_RA6,
TILE_WIRE_RAM_RA7,
TILE_WIRE_RAM_RA8,
TILE_WIRE_RAM_WE0,
TILE_WIRE_RAM_WE1,
TILE_WIRE_RAM_DI0,
TILE_WIRE_RAM_DI1,
TILE_WIRE_RAM_DI2,
TILE_WIRE_RAM_DI3,
TILE_WIRE_RAM_DI4,
TILE_WIRE_RAM_DI5,
TILE_WIRE_RAM_DI6,
TILE_WIRE_RAM_DI7,
TILE_WIRE_RAM_DI8,
TILE_WIRE_RAM_DI9,
TILE_WIRE_RAM_DI10,
TILE_WIRE_RAM_DI11,
TILE_WIRE_RAM_DI12,
TILE_WIRE_RAM_DI13,
TILE_WIRE_RAM_DI14,
TILE_WIRE_RAM_DI15,
TILE_WIRE_RAM_DO0,
TILE_WIRE_RAM_DO1,
TILE_WIRE_RAM_DO2,
TILE_WIRE_RAM_DO3,
TILE_WIRE_RAM_DO4,
TILE_WIRE_RAM_DO5,
TILE_WIRE_RAM_DO6,
TILE_WIRE_RAM_DO7,
TILE_WIRE_RAM_DO8,
TILE_WIRE_RAM_DO9,
TILE_WIRE_RAM_DO10,
TILE_WIRE_RAM_DO11,
TILE_WIRE_RAM_DO12,
TILE_WIRE_RAM_DO13,
TILE_WIRE_RAM_DO14,
TILE_WIRE_RAM_DO15,
};
NEXTPNR_NAMESPACE_END
#endif

123
himbaechel/uarch/example/gfxids.inc Normal file
View File

@ -0,0 +1,123 @@
X(L0_O)
X(L1_O)
X(L2_O)
X(L3_O)
X(L4_O)
X(L5_O)
X(L6_O)
X(L7_O)
X(L0_I0)
X(L0_I1)
X(L0_I2)
X(L0_I3)
X(L1_I0)
X(L1_I1)
X(L1_I2)
X(L1_I3)
X(L2_I0)
X(L2_I1)
X(L2_I2)
X(L2_I3)
X(L3_I0)
X(L3_I1)
X(L3_I2)
X(L3_I3)
X(L4_I0)
X(L4_I1)
X(L4_I2)
X(L4_I3)
X(L5_I0)
X(L5_I1)
X(L5_I2)
X(L5_I3)
X(L6_I0)
X(L6_I1)
X(L6_I2)
X(L6_I3)
X(L7_I0)
X(L7_I1)
X(L7_I2)
X(L7_I3)
X(L0_D)
X(L1_D)
X(L2_D)
X(L3_D)
X(L4_D)
X(L5_D)
X(L6_D)
X(L7_D)
X(L0_Q)
X(L1_Q)
X(L2_Q)
X(L3_Q)
X(L4_Q)
X(L5_Q)
X(L6_Q)
X(L7_Q)
X(RAM_WA0)
X(RAM_WA1)
X(RAM_WA2)
X(RAM_WA3)
X(RAM_WA4)
X(RAM_WA5)
X(RAM_WA6)
X(RAM_WA7)
X(RAM_WA8)
X(RAM_RA0)
X(RAM_RA1)
X(RAM_RA2)
X(RAM_RA3)
X(RAM_RA4)
X(RAM_RA5)
X(RAM_RA6)
X(RAM_RA7)
X(RAM_RA8)
X(RAM_WE0)
X(RAM_WE1)
X(RAM_DI0)
X(RAM_DI1)
X(RAM_DI2)
X(RAM_DI3)
X(RAM_DI4)
X(RAM_DI5)
X(RAM_DI6)
X(RAM_DI7)
X(RAM_DI8)
X(RAM_DI9)
X(RAM_DI10)
X(RAM_DI11)
X(RAM_DI12)
X(RAM_DI13)
X(RAM_DI14)
X(RAM_DI15)
X(RAM_DO0)
X(RAM_DO1)
X(RAM_DO2)
X(RAM_DO3)
X(RAM_DO4)
X(RAM_DO5)
X(RAM_DO6)
X(RAM_DO7)
X(RAM_DO8)
X(RAM_DO9)
X(RAM_DO10)
X(RAM_DO11)
X(RAM_DO12)
X(RAM_DO13)
X(RAM_DO14)
X(RAM_DO15)