From 5cf0c559facae55da997afc23a287b586281d223 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 27 Dec 2018 23:12:57 -0800 Subject: [PATCH] Remove files from tree --- xc7/125MHz_to_60MHz.v | 177 ------------------------------------------ xc7/attosoc.v | 127 ------------------------------ 2 files changed, 304 deletions(-) delete mode 100755 xc7/125MHz_to_60MHz.v delete mode 100644 xc7/attosoc.v diff --git a/xc7/125MHz_to_60MHz.v b/xc7/125MHz_to_60MHz.v deleted file mode 100755 index 72e474d8..00000000 --- a/xc7/125MHz_to_60MHz.v +++ /dev/null @@ -1,177 +0,0 @@ -// file: clk_wiz_v3_6.v -// -// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// "Output Output Phase Duty Pk-to-Pk Phase" -// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" -//---------------------------------------------------------------------------- -// CLK_OUT1____60.000______0.000______50.0______231.736____234.038 -// -//---------------------------------------------------------------------------- -// "Input Clock Freq (MHz) Input Jitter (UI)" -//---------------------------------------------------------------------------- -// __primary_________125.000____________0.010 - -`timescale 1ps/1ps - -(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=8.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *) -module clk_wiz_v3_6 - (// Clock in ports - input CLK_IN1, - // Clock out ports - output CLK_OUT1 - ); - - // Input buffering - //------------------------------------ - assign clkin1 = CLK_IN1; - - - // Clocking primitive - //------------------------------------ - // Instantiation of the MMCM primitive - // * Unused inputs are tied off - // * Unused outputs are labeled unused - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_unused; - wire clkfbout; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (5), - .CLKFBOUT_MULT_F (40.500), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (16.875), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (8.000), - .REF_JITTER1 (0.010)) - mmcm_adv_inst - // Output clocks - (.CLKFBOUT (clkfbout), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (clkout0), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clkout1_unused), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout), - .CLKIN1 (clkin1), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_unused), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (1'b0)); - - // Output buffering - //----------------------------------- - - //BUFG clkout1_buf - // (.O (CLK_OUT1), - // .I (clkout0)); - - // BUFG not currently supported - BUFGCTRL clkout1_buf ( - .I0(clkout0), - .CE0(1'b1), - .S0(1'b1), - .O(CLK_OUT1) - ); - - - -endmodule diff --git a/xc7/attosoc.v b/xc7/attosoc.v deleted file mode 100644 index 4921e298..00000000 --- a/xc7/attosoc.v +++ /dev/null @@ -1,127 +0,0 @@ -/* - * ECP5 PicoRV32 demo - * - * Copyright (C) 2017 Clifford Wolf - * Copyright (C) 2018 David Shah - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -`ifdef PICORV32_V -`error "attosoc.v must be read before picorv32.v!" -`endif - -`define PICORV32_REGS picosoc_regs - -module attosoc ( - input clk, - output reg [7:0] led -); - - reg [5:0] reset_cnt = 0; - wire resetn = &reset_cnt; - - always @(posedge clk) begin - reset_cnt <= reset_cnt + !resetn; - end - - parameter integer MEM_WORDS = 256; - parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory - parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // ROM at 0x0 - parameter integer ROM_BYTES = 256; - - reg [7:0] rom [0:ROM_BYTES-1]; - wire [31:0] rom_rdata = {rom[mem_addr+3], rom[mem_addr+2], rom[mem_addr+1], rom[mem_addr+0]}; - initial $readmemh("firmware.hex", rom); - - wire mem_valid; - wire mem_instr; - wire mem_ready; - wire [31:0] mem_addr; - wire [31:0] mem_wdata; - wire [3:0] mem_wstrb; - wire [31:0] mem_rdata; - - wire rom_ready = mem_valid && mem_addr[31:24] == 8'h00; - - wire iomem_valid; - wire iomem_ready; - wire [31:0] iomem_addr; - wire [31:0] iomem_wdata; - wire [3:0] iomem_wstrb; - wire [31:0] iomem_rdata; - - assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01); - assign iomem_ready = 1'b1; - assign iomem_wstrb = mem_wstrb; - assign iomem_addr = mem_addr; - assign iomem_wdata = mem_wdata; - - wire [31:0] spimemio_cfgreg_do; - - - always @(posedge clk) - if (iomem_valid && iomem_wstrb[0]) - led <= iomem_wdata[7:0]; - - assign mem_ready = (iomem_valid && iomem_ready) || rom_ready; - - assign mem_rdata = rom_rdata; - - picorv32 #( - .STACKADDR(STACKADDR), - .PROGADDR_RESET(PROGADDR_RESET), - .PROGADDR_IRQ(32'h 0000_0000), - .BARREL_SHIFTER(0), - .COMPRESSED_ISA(0), - .ENABLE_MUL(0), - .ENABLE_DIV(0), - .ENABLE_IRQ(0), - .ENABLE_IRQ_QREGS(0) - ) cpu ( - .clk (clk ), - .resetn (resetn ), - .mem_valid (mem_valid ), - .mem_instr (mem_instr ), - .mem_ready (mem_ready ), - .mem_addr (mem_addr ), - .mem_wdata (mem_wdata ), - .mem_wstrb (mem_wstrb ), - .mem_rdata (mem_rdata ) - ); - - - -endmodule - -// Implementation note: -// Replace the following two modules with wrappers for your SRAM cells. - -module picosoc_regs ( - input clk, wen, - input [5:0] waddr, - input [5:0] raddr1, - input [5:0] raddr2, - input [31:0] wdata, - output [31:0] rdata1, - output [31:0] rdata2 -); - reg [31:0] regs [0:31]; - - always @(posedge clk) - if (wen) regs[waddr[4:0]] <= wdata; - - assign rdata1 = regs[raddr1[4:0]]; - assign rdata2 = regs[raddr2[4:0]]; -endmodule