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return FF_USED, formatting, correct INIT

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This commit is contained in:
Pepijn de Vos 2019-11-08 17:15:12 +01:00
parent 7c362f292c
commit 5dd1e5e51e
4 changed files with 20 additions and 5 deletions
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3
.gitignore vendored
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@ -19,6 +19,9 @@ CMakeCache.txt
.*.swp
a.out
*.json
*.dot
*.il
/generic/examples/blinky.png
build/
*.asc
*.bin

14
generic/cells.cc
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@ -42,8 +42,9 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
}
new_cell->type = type;
if (type == ctx->id("GENERIC_SLICE")) {
new_cell->params[ctx->id("K")] = std::to_string(ctx->args.K);
new_cell->params[ctx->id("K")] = ctx->args.K;
new_cell->params[ctx->id("INIT")] = 0;
new_cell->params[ctx->id("FF_USED")] = 0;
for (int i = 0; i < ctx->args.K; i++)
add_port(ctx, new_cell.get(), "I[" + std::to_string(i) + "]", PORT_IN);
@ -80,16 +81,25 @@ void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
}
if (no_dff) {
lc->params[ctx->id("FF_USED")] = 0;
replace_port(lut, ctx->id("Q"), lc, ctx->id("F"));
}
}
void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
{
lc->params[ctx->id("FF_USED")] = 1;
replace_port(dff, ctx->id("CLK"), lc, ctx->id("CLK"));
if (pass_thru_lut) {
lc->params[ctx->id("INIT")] = 0xAAAA;
// Fill LUT with alternating 10
const int init_size = 1 << lc->params[ctx->id("K")].as_int64();
std::string init;
init.reserve(init_size);
for(int i = 0; i < init_size; i+=2)
init.append("10");
lc->params[ctx->id("INIT")] = Property::from_string(init);
replace_port(dff, ctx->id("D"), lc, ctx->id("I[0]"));
}

1
generic/examples/bitstream.py
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@ -6,6 +6,7 @@ from simple_config import K
param_map = {
("GENERIC_SLICE", "K"): ParameterConfig(write=False),
("GENERIC_SLICE", "INIT"): ParameterConfig(write=True, numeric=True, width=2**K),
("GENERIC_SLICE", "FF_USED"): ParameterConfig(write=True, numeric=True, width=1),
("GENERIC_IOB", "INPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),
("GENERIC_IOB", "OUTPUT_USED"): ParameterConfig(write=True, numeric=True, width=1),

7
generic/synth/prims.v
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@ -21,19 +21,20 @@ endmodule
module GENERIC_SLICE #(
parameter K = 4,
parameter [2**K-1:0] INIT = 0,
parameter FF_USED = 1'b0
) (
input CLK,
input [K-1:0] I,
output F,
output Q
);
wire f_wire;
wire f_wire;
LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
assign F = f_wire;
assign F = f_wire;
endmodule
module GENERIC_IOB #(