Add attosoc.sh and attosoc_tb.vhd

xc7/attosoc.sh

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+#!/bin/bash
+#set -ex
+#rm -f picorv32.v
+#wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
+yosys attosoc.ys
+../nextpnr-xc7 --json attosoc.json --xdl attosoc.xdl --pcf attosoc.pcf --freq 150
+xdl -xdl2ncd attosoc.xdl
+bitgen -w attosoc.ncd -g UnconstrainedPins:Allow
+trce attosoc.ncd -v 10
+
+netgen -sim -ofmt vhdl attosoc.ncd attosoc_pnr.vhd
+ghdl -c -fexplicit --no-vital-checks --ieee=synopsys -Pxilinx-ise attosoc_tb.vhd attosoc_pnr.vhd -r testbench

xc7/attosoc_tb.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity testbench is
+end entity;
+architecture rtl of testbench is
+    signal clk : STD_LOGIC;
+    signal led : STD_LOGIC_VECTOR(3 downto 0);
+begin
+    process begin
+        clk <= '0';
+        wait for 4 ns;
+        clk <= '1';
+        wait for 4 ns;
+    end process;
+
+    uut: entity work.name port map(clk_PAD_PAD => clk, led_0_OUTBUF_OUT => led(0), led_1_OUTBUF_OUT => led(1), led_2_OUTBUF_OUT => led(2), led_3_OUTBUF_OUT => led(3));
+
+process
+begin
+report std_logic'image(led(3)) & std_logic'image(led(2)) & std_logic'image(led(1)) & std_logic'image(led(0));
+wait on led;
+end process;
+
+end rtl;