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Merge pull request #581 from litghost/add_isbelhidden

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Add getBelHidden and add some missing "override" statements.
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gatecat 2021-02-12 09:53:50 +00:00 committed by GitHub
commit 5dfbe703ae
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11 changed files with 30 additions and 16 deletions
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4
common/design_utils.cc
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@ -71,7 +71,9 @@ void print_utilisation(const Context *ctx)
} }
std::map<IdString, int> available_types; std::map<IdString, int> available_types;
for (auto bel : ctx->getBels()) { for (auto bel : ctx->getBels()) {
available_types[ctx->getBelType(bel)]++; if (!ctx->getBelHidden(bel)) {
available_types[ctx->getBelType(bel)]++;
}
} }
log_break(); log_break();
log_info("Device utilisation:\n"); log_info("Device utilisation:\n");

7
common/nextpnr.h
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@ -1089,6 +1089,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual CellInfo *getBoundBelCell(BelId bel) const = 0; virtual CellInfo *getBoundBelCell(BelId bel) const = 0;
virtual CellInfo *getConflictingBelCell(BelId bel) const = 0; virtual CellInfo *getConflictingBelCell(BelId bel) const = 0;
virtual IdString getBelType(BelId bel) const = 0; virtual IdString getBelType(BelId bel) const = 0;
virtual bool getBelHidden(BelId bel) const = 0;
virtual typename R::BelAttrsRangeT getBelAttrs(BelId bel) const = 0; virtual typename R::BelAttrsRangeT getBelAttrs(BelId bel) const = 0;
virtual WireId getBelPinWire(BelId bel, IdString pin) const = 0; virtual WireId getBelPinWire(BelId bel, IdString pin) const = 0;
virtual PortType getBelPinType(BelId bel, IdString pin) const = 0; virtual PortType getBelPinType(BelId bel, IdString pin) const = 0;
@ -1201,7 +1202,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
// Basic config // Basic config
virtual IdString archId() const override { return this->id(STRINGIFY(ARCHNAME)); } virtual IdString archId() const override { return this->id(STRINGIFY(ARCHNAME)); }
virtual IdString archArgsToId(typename R::ArchArgsT args) const { return IdString(); } virtual IdString archArgsToId(typename R::ArchArgsT args) const override { return IdString(); }
virtual int getTilePipDimZ(int x, int y) const override { return 1; } virtual int getTilePipDimZ(int x, int y) const override { return 1; }
virtual char getNameDelimiter() const override { return ' '; } virtual char getNameDelimiter() const override { return ' '; }
@ -1228,6 +1229,8 @@ template <typename R> struct BaseArch : ArchAPI<R>
this->refreshUiBel(bel); this->refreshUiBel(bel);
} }
virtual bool getBelHidden(BelId bel) const override { return false; }
virtual bool getBelGlobalBuf(BelId bel) const override { return false; } virtual bool getBelGlobalBuf(BelId bel) const override { return false; }
virtual bool checkBelAvail(BelId bel) const override { return getBoundBelCell(bel) == nullptr; }; virtual bool checkBelAvail(BelId bel) const override { return getBoundBelCell(bel) == nullptr; };
virtual CellInfo *getBoundBelCell(BelId bel) const override virtual CellInfo *getBoundBelCell(BelId bel) const override
@ -1290,7 +1293,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
virtual NetInfo *getConflictingWireNet(WireId wire) const override { return getBoundWireNet(wire); } virtual NetInfo *getConflictingWireNet(WireId wire) const override { return getBoundWireNet(wire); }
// Pip methods // Pip methods
virtual IdString getPipType(PipId pip) const { return IdString(); } virtual IdString getPipType(PipId pip) const override { return IdString(); }
virtual typename R::PipAttrsRangeT getPipAttrs(PipId) const override virtual typename R::PipAttrsRangeT getPipAttrs(PipId) const override
{ {
return empty_if_possible<typename R::PipAttrsRangeT>(); return empty_if_possible<typename R::PipAttrsRangeT>();

6
docs/archapi.md
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@ -225,6 +225,12 @@ Return a list of all bels on the device.
Return the type of a given bel. Return the type of a given bel.
### bool getBelHidden(BelId bel) const
Should this bel be hidden from utilities?
*BaseArch default: returns false*
### BelAttrsRangeT getBelAttrs(BelId bel) const ### BelAttrsRangeT getBelAttrs(BelId bel) const
Return the attributes for that bel. Bel attributes are only informal. They are displayed by the GUI but are otherwise Return the attributes for that bel. Bel attributes are only informal. They are displayed by the GUI but are otherwise

2
ecp5/arch.h
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@ -601,7 +601,7 @@ struct Arch : BaseArch<ArchRanges>
return range; return range;
} }
std::vector<IdString> getBelPins(BelId bel) const; std::vector<IdString> getBelPins(BelId bel) const override;
// ------------------------------------------------- // -------------------------------------------------

3
fpga_interchange/arch.h
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@ -824,8 +824,7 @@ struct Arch : ArchAPI<ArchRanges>
return false; return false;
} }
// TODO: this needs to become part of the Arch API bool getBelHidden(BelId bel) const override { return bel_info(chip_info, bel).category != BEL_CATEGORY_LOGIC; }
bool getBelHidden(BelId bel) const { return bel_info(chip_info, bel).category != BEL_CATEGORY_LOGIC; }
IdString getBelType(BelId bel) const override IdString getBelType(BelId bel) const override
{ {

5
generic/arch.cc
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@ -91,7 +91,7 @@ void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStri
tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1); tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
} }
void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb) void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden)
{ {
NPNR_ASSERT(bels.count(name) == 0); NPNR_ASSERT(bels.count(name) == 0);
NPNR_ASSERT(bel_by_loc.count(loc) == 0); NPNR_ASSERT(bel_by_loc.count(loc) == 0);
@ -102,6 +102,7 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb)
bi.y = loc.y; bi.y = loc.y;
bi.z = loc.z; bi.z = loc.z;
bi.gb = gb; bi.gb = gb;
bi.hidden = hidden;
bel_ids.push_back(name); bel_ids.push_back(name);
bel_by_loc[loc] = name; bel_by_loc[loc] = name;
@ -319,6 +320,8 @@ const std::vector<BelId> &Arch::getBels() const { return bel_ids; }
IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; } IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
bool Arch::getBelHidden(BelId bel) const { return bels.at(bel).hidden; }
const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; } const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; }
WireId Arch::getBelPinWire(BelId bel, IdString pin) const WireId Arch::getBelPinWire(BelId bel, IdString pin) const

4
generic/arch.h
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@ -77,6 +77,7 @@ struct BelInfo
DecalXY decalxy; DecalXY decalxy;
int x, y, z; int x, y, z;
bool gb; bool gb;
bool hidden;
}; };
struct GroupInfo struct GroupInfo
@ -177,7 +178,7 @@ struct Arch : ArchAPI<ArchRanges>
void addWire(IdStringList name, IdString type, int x, int y); void addWire(IdStringList name, IdString type, int x, int y);
void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay, Loc loc); void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay, Loc loc);
void addBel(IdStringList name, IdString type, Loc loc, bool gb); void addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
void addBelInput(IdStringList bel, IdString name, IdStringList wire); void addBelInput(IdStringList bel, IdString name, IdStringList wire);
void addBelOutput(IdStringList bel, IdString name, IdStringList wire); void addBelOutput(IdStringList bel, IdString name, IdStringList wire);
void addBelInout(IdStringList bel, IdString name, IdStringList wire); void addBelInout(IdStringList bel, IdString name, IdStringList wire);
@ -237,6 +238,7 @@ struct Arch : ArchAPI<ArchRanges>
CellInfo *getConflictingBelCell(BelId bel) const override; CellInfo *getConflictingBelCell(BelId bel) const override;
const std::vector<BelId> &getBels() const override; const std::vector<BelId> &getBels() const override;
IdString getBelType(BelId bel) const override; IdString getBelType(BelId bel) const override;
bool getBelHidden(BelId bel) const override;
const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override; const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override;
WireId getBelPinWire(BelId bel, IdString pin) const override; WireId getBelPinWire(BelId bel, IdString pin) const override;
PortType getBelPinType(BelId bel, IdString pin) const override; PortType getBelPinType(BelId bel, IdString pin) const override;

7
generic/arch_pybindings.cc
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@ -162,10 +162,9 @@ void arch_wrap_python(py::module &m)
pass_through<DelayInfo>, pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a, pass_through<DelayInfo>, pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a,
"srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a); "srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a);
fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>, fn_wrapper_5a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>,
conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel", conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>,
"name"_a, "type"_a, pass_through<bool>>::def_wrap(ctx_cls, "addBel", "name"_a, "type"_a, "loc"_a, "gb"_a, "hidden"_a);
"loc"_a, "gb"_a);
fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdStringList>, fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdStringList>,
conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInput", "bel"_a, conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
"name"_a, "wire"_a); "name"_a, "wire"_a);

4
generic/examples/simple.py
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@ -20,13 +20,13 @@ for x in range(X):
if x == y: if x == y:
continue continue
for z in range(2): for z in range(2):
ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False) ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False, hidden=False)
ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z)) ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z))
ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z)) ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z))
ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z)) ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z))
else: else:
for z in range(N): for z in range(N):
ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False) ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False, hidden=False)
ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z)) ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z))
for k in range(K): for k in range(K):
ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k)) ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k))

2
ice40/arch.h
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@ -849,7 +849,7 @@ struct Arch : BaseArch<ArchRanges>
// Assign architecture-specific arguments to nets and cells, which must be // Assign architecture-specific arguments to nets and cells, which must be
// called between packing or further // called between packing or further
// netlist modifications, and validity checks // netlist modifications, and validity checks
void assignArchInfo(); void assignArchInfo() override;
void assignCellInfo(CellInfo *cell); void assignCellInfo(CellInfo *cell);
// ------------------------------------------------- // -------------------------------------------------

2
nexus/arch.h
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@ -1118,7 +1118,7 @@ struct Arch : BaseArch<ArchRanges>
WireId getPipSrcWire(PipId pip) const override { return canonical_wire(pip.tile, pip_data(pip).from_wire); } WireId getPipSrcWire(PipId pip) const override { return canonical_wire(pip.tile, pip_data(pip).from_wire); }
WireId getPipDstWire(PipId pip) const { return canonical_wire(pip.tile, pip_data(pip).to_wire); } WireId getPipDstWire(PipId pip) const override { return canonical_wire(pip.tile, pip_data(pip).to_wire); }
DelayInfo getPipDelay(PipId pip) const override DelayInfo getPipDelay(PipId pip) const override
{ {