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ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE

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This requires the matching chipdb update from icestorm project !

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2020-06-02 11:02:48 +02:00
parent f44498a530
commit 5e2b6bcef9
1 changed files with 1 additions and 1 deletions
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2
ice40/bitstream.cc
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@ -718,7 +718,7 @@ void write_asc(const Context *ctx, std::ostream &out)
{"PLLOUT_SELECT_A", 2},
{"PLLOUT_SELECT_B", 2},
{"PLLTYPE", 3},
{"SHIFTREG_DIV_MODE", 1},
{"SHIFTREG_DIV_MODE", 2},
{"TEST_MODE", 1}};
configure_extra_cell(config, ctx, cell.second.get(), pll_params, false, std::string("PLL."));