From 5e2b6bcef945a89daa215d01e15120162f81da7b Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Tue, 2 Jun 2020 11:02:48 +0200 Subject: [PATCH] ice40: Add support for the 2nd bit of SHIFTREG_DIV_MODE This requires the matching chipdb update from icestorm project ! Signed-off-by: Sylvain Munaut --- ice40/bitstream.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 9586b8ff..3865316f 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -718,7 +718,7 @@ void write_asc(const Context *ctx, std::ostream &out) {"PLLOUT_SELECT_A", 2}, {"PLLOUT_SELECT_B", 2}, {"PLLTYPE", 3}, - {"SHIFTREG_DIV_MODE", 1}, + {"SHIFTREG_DIV_MODE", 2}, {"TEST_MODE", 1}}; configure_extra_cell(config, ctx, cell.second.get(), pll_params, false, std::string("PLL."));