diff --git a/common/design.h b/common/design.h new file mode 100644 index 00000000..421937eb --- /dev/null +++ b/common/design.h @@ -0,0 +1,95 @@ +/* + * nextpnr -- Next Generation PnR + * + * Copyright (C) 2018 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef DESIGN_H +#define DESIGN_H + +#include +#include +#include +#include +#include + +// replace with proper IdString later +typedef std::string IdString; + +// replace with haslib later +template using pool = std::unordered_set; +template using dict = std::unordered_map; +using std::vector; + +#include "chip.h" + +struct CellInfo; + +struct PortRef +{ + CellInfo *cell; + IdString port; +}; + +struct NetInfo +{ + IdString name; + PortRef driver; + vector users; + dict attrs; + + // wire -> (uphill_wire, delay) + dict> wires; +}; + +enum PortType +{ + PORT_IN = 0, + PORT_OUT = 1, + PORT_INOUT = 2 +}; + +struct PortInfo +{ + IdString name; + NetInfo *net; + PortType type; +}; + +struct CellInfo +{ + IdString name, type; + dict ports; + dict attrs, params; + + BelId bel; + // cell_port -> bel_pin + dict pins; +}; + +struct Design +{ + struct Chip chip; + + Design(ChipArgs args) : chip(args) { + // ... + } + + dict nets; + dict cells; +}; + +#endif diff --git a/database.cc b/dummy/chip.cc similarity index 87% rename from database.cc rename to dummy/chip.cc index 1dbff97b..58b55ec9 100644 --- a/database.cc +++ b/dummy/chip.cc @@ -1,4 +1,4 @@ -#include "database.h" +#include "chip.h" Chip::Chip(ChipArgs) { diff --git a/database.h b/dummy/chip.h similarity index 74% rename from database.h rename to dummy/chip.h index a859ef1a..07202e22 100644 --- a/database.h +++ b/dummy/chip.h @@ -1,19 +1,26 @@ -#include -#include -#include -#include -#include +/* + * nextpnr -- Next Generation PnR + * + * Copyright (C) 2018 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ -// replace with proper IdString later -typedef std::string IdString; +#include "design.h" -// replace with haslib later -template using pool = std::unordered_set; -template using dict = std::unordered_map; -using std::vector; - -// ------------------------------------------------------- -// Arch-specific declarations +#ifndef CHIP_H +#define CHIP_H struct BelId { @@ -182,61 +189,4 @@ struct Chip BelPinRange getBelPinsDownhill(WireId wire) const; }; -// ------------------------------------------------------- -// Generic declarations - -struct CellInfo; - -struct PortRef -{ - CellInfo *cell; - IdString port; -}; - -struct NetInfo -{ - IdString name; - PortRef driver; - vector users; - dict attrs; - - // wire -> (uphill_wire, delay) - dict> wires; -}; - -enum PortType -{ - PORT_IN = 0, - PORT_OUT = 1, - PORT_INOUT = 2 -}; - -struct PortInfo -{ - IdString name; - NetInfo *net; - PortType type; -}; - -struct CellInfo -{ - IdString name, type; - dict ports; - dict attrs, params; - - BelId bel; - // cell_port -> bel_pin - dict pins; -}; - -struct Design -{ - struct Chip chip; - - Design(ChipArgs args) : chip(args) { - // ... - } - - dict nets; - dict cells; -}; +#endif diff --git a/demo.cc b/dummy/main.cc similarity index 73% rename from demo.cc rename to dummy/main.cc index 665724b0..01050d24 100644 --- a/demo.cc +++ b/dummy/main.cc @@ -1,5 +1,3 @@ -// clang -o demo -Wall -std=c++11 demo.cc database.cc -lstdc++ - #include "database.h" int main()