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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-05-26 10:47:35 +02:00
parent 75ae343e1f
commit 5e48758b30
4 changed files with 118 additions and 75 deletions
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95
common/design.h Normal file
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@ -0,0 +1,95 @@
/*
* nextpnr -- Next Generation PnR
*
* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef DESIGN_H
#define DESIGN_H
#include <stdint.h>
#include <vector>
#include <string>
#include <unordered_set>
#include <unordered_map>
// replace with proper IdString later
typedef std::string IdString;
// replace with haslib later
template<typename T> using pool = std::unordered_set<T>;
template<typename T, typename U> using dict = std::unordered_map<T, U>;
using std::vector;
#include "chip.h"
struct CellInfo;
struct PortRef
{
CellInfo *cell;
IdString port;
};
struct NetInfo
{
IdString name;
PortRef driver;
vector<PortRef> users;
dict<IdString, std::string> attrs;
// wire -> (uphill_wire, delay)
dict<WireId, std::pair<WireId, float>> wires;
};
enum PortType
{
PORT_IN = 0,
PORT_OUT = 1,
PORT_INOUT = 2
};
struct PortInfo
{
IdString name;
NetInfo *net;
PortType type;
};
struct CellInfo
{
IdString name, type;
dict<IdString, PortInfo> ports;
dict<IdString, std::string> attrs, params;
BelId bel;
// cell_port -> bel_pin
dict<IdString, IdString> pins;
};
struct Design
{
struct Chip chip;
Design(ChipArgs args) : chip(args) {
// ...
}
dict<IdString, NetInfo*> nets;
dict<IdString, CellInfo*> cells;
};
#endif

2
database.cc → dummy/chip.cc
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@ -1,4 +1,4 @@
#include "database.h"
#include "chip.h"
Chip::Chip(ChipArgs)
{

94
database.h → dummy/chip.h
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@ -1,19 +1,26 @@
#include <stdint.h>
#include <vector>
#include <string>
#include <unordered_set>
#include <unordered_map>
/*
* nextpnr -- Next Generation PnR
*
* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// replace with proper IdString later
typedef std::string IdString;
#include "design.h"
// replace with haslib later
template<typename T> using pool = std::unordered_set<T>;
template<typename T, typename U> using dict = std::unordered_map<T, U>;
using std::vector;
// -------------------------------------------------------
// Arch-specific declarations
#ifndef CHIP_H
#define CHIP_H
struct BelId
{
@ -182,61 +189,4 @@ struct Chip
BelPinRange getBelPinsDownhill(WireId wire) const;
};
// -------------------------------------------------------
// Generic declarations
struct CellInfo;
struct PortRef
{
CellInfo *cell;
IdString port;
};
struct NetInfo
{
IdString name;
PortRef driver;
vector<PortRef> users;
dict<IdString, std::string> attrs;
// wire -> (uphill_wire, delay)
dict<WireId, std::pair<WireId, float>> wires;
};
enum PortType
{
PORT_IN = 0,
PORT_OUT = 1,
PORT_INOUT = 2
};
struct PortInfo
{
IdString name;
NetInfo *net;
PortType type;
};
struct CellInfo
{
IdString name, type;
dict<IdString, PortInfo> ports;
dict<IdString, std::string> attrs, params;
BelId bel;
// cell_port -> bel_pin
dict<IdString, IdString> pins;
};
struct Design
{
struct Chip chip;
Design(ChipArgs args) : chip(args) {
// ...
}
dict<IdString, NetInfo*> nets;
dict<IdString, CellInfo*> cells;
};
#endif

2
demo.cc → dummy/main.cc
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@ -1,5 +1,3 @@
// clang -o demo -Wall -std=c++11 demo.cc database.cc -lstdc++
#include "database.h"
int main()