mistral: Updated CLK mux select name

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2022-03-18 18:54:12 +00:00
parent 051228c49a
commit 5e9236f9d4
2 changed files with 2 additions and 2 deletions

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@ -21,7 +21,7 @@ jobs:
- name: Execute build nextpnr - name: Execute build nextpnr
env: env:
MISTRAL_PATH: ${{ github.workspace }}/deps/mistral MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
MISTRAL_REVISION: 6b0ce163d87200d0d5b7f330349aacf886f0f8be MISTRAL_REVISION: ebfc0dd2cc7d6d2159b641a397c88554840e93c9
run: | run: |
source ./.github/ci/build_mistral.sh source ./.github/ci/build_mistral.sh
get_dependencies get_dependencies

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@ -114,7 +114,7 @@ struct MistralBitgen
{ {
(void)ci; // currently unused (void)ci; // currently unused
auto pos = CycloneV::xy2pos(x, y); auto pos = CycloneV::xy2pos(x, y);
cv->bmux_r_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SELECT, bi, 0x1b); // hardcode to general routing cv->bmux_r_set(CycloneV::CMUXHG, pos, CycloneV::INPUT_SEL, bi, 0x1b); // hardcode to general routing
cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB); cv->bmux_m_set(CycloneV::CMUXHG, pos, CycloneV::TESTSYN_ENOUT_SELECT, bi, CycloneV::PRE_SYNENB);
} }