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Merge in vx980t support

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This commit is contained in:
Eddie Hung 2018-12-06 20:07:51 +00:00
parent 20f0353f76
commit 5f75a8447f
7 changed files with 45 additions and 11 deletions
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2
common/place_common.cc
View File

@ -37,6 +37,8 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
if (driver_gb)
return 0;
int clock_count;
if (ctx->getPortTimingClass(driver_cell, net->driver.port, clock_count) == TMG_IGNORE)
return 0;
bool timing_driven = ctx->timing_driven && type == MetricType::COST &&
ctx->getPortTimingClass(driver_cell, net->driver.port, clock_count) != TMG_IGNORE;
delay_t negative_slack = 0;

10
xc7/arch.cc
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@ -102,6 +102,12 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
bel_to_loc.emplace_back(x, y, 0);
site_index_to_bel[i] = b;
++b.index;
} else if (type == "IOB18S" || type == "IOB18M") {
bel_to_site_index.push_back(i);
site_index_to_type[i] = id_IOB18;
bel_to_loc.emplace_back(x, y, 0);
site_index_to_bel[i] = b;
++b.index;
} else {
bel_to_site_index.push_back(i);
site_index_to_type[i] = ctx->id(type);
@ -337,6 +343,8 @@ Arch::Arch(ArchArgs args) : args(args)
}
#endif
}
} else if (args.type == ArchArgs::VX980) {
torc_info = std::unique_ptr<TorcInfo>(new TorcInfo(this, "xc7vx980t", args.package));
} else {
log_error("Unsupported XC7 chip type.\n");
}
@ -922,7 +930,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
}
// TODO
// if (port == id_OMUX)
} else if (cell->type == id_IOB33) {
} else if (cell->type == id_IOB33 || cell->type == id_IOB18) {
if (port == id_I)
return TMG_STARTPOINT;
else if (port == id_O)

3
xc7/arch.h
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@ -489,7 +489,8 @@ struct ArchArgs
enum ArchArgsTypes
{
NONE,
Z020
Z020,
VX980
} type = NONE;
std::string package;
};

14
xc7/cells.cc
View File

@ -70,11 +70,15 @@ std::unique_ptr<CellInfo> create_xc7_cell(Context *ctx, IdString type, std::stri
add_port(ctx, new_cell.get(), "OMUX", PORT_OUT);
add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
} else if (type == ctx->id("IOBUF")) {
new_cell->type = id_IOB33;
new_cell->params[ctx->id("PIN_TYPE")] = "0";
new_cell->params[ctx->id("PULLUP")] = "0";
new_cell->params[ctx->id("NEG_TRIGGER")] = "0";
new_cell->params[ctx->id("IOSTANDARD")] = "SB_LVCMOS";
if (ctx->args.type == ArchArgs::Z020) {
new_cell->type = id_IOB33;
} else {
new_cell->type = id_IOB18;
}
//new_cell->params[ctx->id("PIN_TYPE")] = "0";
//new_cell->params[ctx->id("PULLUP")] = "0";
//new_cell->params[ctx->id("NEG_TRIGGER")] = "0";
//new_cell->params[ctx->id("IOSTANDARD")] = "SB_LVCMOS";
// add_port(ctx, new_cell.get(), "PACKAGE_PIN", PORT_INOUT);
//

1
xc7/constids.inc
View File

@ -458,5 +458,6 @@ X(FDPE)
X(BUFGCTRL)
X(SLICE_LUT6)
X(IOB33)
X(IOB18)
X(PS7)
X(MMCME2_ADV)

11
xc7/main.cc
View File

@ -51,8 +51,9 @@ Xc7CommandHandler::Xc7CommandHandler(int argc, char **argv) : CommandHandler(arg
po::options_description Xc7CommandHandler::getArchOptions()
{
po::options_description specific("Architecture specific options");
specific.add_options()("xc7z020", "set device type to xc7z020");
// specific.add_options()("package", po::value<std::string>(), "set device package");
specific.add_options()("z020", "set device type to xc7z020");
specific.add_options()("vx980", "set device type to xc7v980");
specific.add_options()("package", po::value<std::string>(), "set device package");
specific.add_options()("pcf", po::value<std::string>(), "PCF constraints file to ingest");
specific.add_options()("xdl", po::value<std::string>(), "XDL file to write");
// specific.add_options()("tmfuzz", "run path delay estimate fuzzer");
@ -97,6 +98,12 @@ std::unique_ptr<Context> Xc7CommandHandler::createContext()
chipArgs.package = "clg400";
}
if (vm.count("vx980")) {
chipArgs.type = ArchArgs::VX980;
chipArgs.package = "ffg1926";
}
if (chipArgs.type == ArchArgs::NONE) {
chipArgs.type = ArchArgs::Z020;
chipArgs.package = "clg400";

15
xc7/xdl.cc
View File

@ -68,7 +68,7 @@ void write_xdl(const Context *ctx, std::ostream &out)
const char *type;
if (cell.second->type == id_SLICE_LUT6)
type = "SLICEL";
else if (cell.second->type == id_IOB33 || cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7 || cell.second->type == id_MMCME2_ADV)
else if (cell.second->type == id_IOB33 || cell.second->type == id_IOB18 || cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7 || cell.second->type == id_MMCME2_ADV)
type = cell.second->type.c_str(ctx);
else
log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
@ -111,7 +111,7 @@ void write_xdl(const Context *ctx, std::ostream &out)
// Assume from Yosys that INIT masks of less than 32 bits are output as uint32_t
if (lut_inputs.size() < 6) {
auto init_as_uint = boost::lexical_cast<uint32_t>(init);
NPNR_ASSERT(init_as_uint < (1ull << (1u << lut_inputs.size())));
NPNR_ASSERT(init_as_uint <= (1ull << (1u << lut_inputs.size())));
if (lut_inputs.empty())
value += init;
else {
@ -198,6 +198,17 @@ void write_xdl(const Context *ctx, std::ostream &out)
} else if (cell.second->type == id_BUFGCTRL || cell.second->type == id_PS7 || cell.second->type == id_MMCME2_ADV) {
for (const auto& i : cell.second->params)
instPtr->setConfig(i.first.str(ctx), "", i.second);
} else if (cell.second->type == id_IOB18) {
if (get_net_or_empty(cell.second.get(), id_I)) {
instPtr->setConfig("IUSED", "", "0");
instPtr->setConfig("IBUF_LOW_PWR", "", "TRUE");
instPtr->setConfig("ISTANDARD", "", "LVCMOS18");
} else {
instPtr->setConfig("OUSED", "", "0");
instPtr->setConfig("OSTANDARD", "", "LVCMOS18");
instPtr->setConfig("DRIVE", "", "12");
instPtr->setConfig("SLEW", "", "SLOW");
}
} else
log_error("Unsupported cell type '%s'.\n", cell.second->type.c_str(ctx));
}