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ice40: Adding cell utilities for packing

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-12 11:49:54 +02:00
parent 3ce32b6b1d
commit 5f813410aa
4 changed files with 191 additions and 15 deletions
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32
common/design_utils.cc
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@ -19,22 +19,30 @@
#include "design_utils.h"
void replace_port(CellInfo *old_cell, PortInfo *old, CellInfo *rep_cell,
PortInfo *rep)
void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
IdString rep_name)
{
assert(old->type == rep->type);
PortInfo &old = old_cell->ports.at(old_name);
PortInfo &rep = rep_cell->ports.at(rep_name);
assert(old.type == rep.type);
rep->net = old->net;
old->net = nullptr;
if (rep->type == PORT_OUT) {
rep->net->driver.cell = rep_cell;
rep->net->driver.port = rep->name;
} else if (rep->type == PORT_IN) {
for (PortRef &load : rep->net->users) {
if (load.cell == old_cell && load.port == old->name) {
rep.net = old.net;
old.net = nullptr;
if (rep.type == PORT_OUT) {
if (rep.net != nullptr) {
rep.net->driver.cell = rep_cell;
rep.net->driver.port = rep_name;
}
} else if (rep.type == PORT_IN) {
if (rep.net != nullptr) {
for (PortRef &load : rep.net->users) {
if (load.cell == old_cell && load.port == old_name) {
load.cell = rep_cell;
load.port = rep->name;
load.port = rep_name;
}
}
}
} else {
assert(false);
}
}

8
common/design_utils.h
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@ -19,13 +19,15 @@
#include "nextpnr.h"
#ifndef DESIGN_UTILS_H
#define DESIGN_UTILS_H
/*
Utilities for design manipulation, intended for use inside packing algorithms
*/
// Disconnect a net (if connected) from old, and connect it to rep
void replace_port(CellInfo *old_cell, PortInfo *old, CellInfo *rep_cell,
PortInfo *rep);
void replace_port(CellInfo *old_cell, IdString old_name, CellInfo *rep_cell,
IdString rep_name);
// If a net drives a given port of a cell matching a predicate (in many
// cases more than one cell type, e.g. SB_DFFxx so a predicate is used), return
@ -58,3 +60,5 @@ CellInfo *net_driven_by(NetInfo *net, F1 cell_pred, IdString port)
return nullptr;
}
}
#endif

110
ice40/cells.cc Normal file
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@ -0,0 +1,110 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "cells.h"
#include "design_utils.h"
#include "log.h"
static void add_port(CellInfo *cell, IdString name, PortType dir)
{
cell->ports[name] = PortInfo{name, nullptr, dir};
}
CellInfo *create_ice_cell(Design *design, IdString type, IdString name)
{
static int auto_idx = 0;
CellInfo *new_cell = new CellInfo();
if (name == IdString()) {
new_cell->name =
IdString("$nextpnr_" + type + "_" + std::to_string(auto_idx++));
} else {
new_cell->name = name;
}
if (type == "ICESTORM_LC") {
new_cell->params["LUT_INIT"] = "0";
new_cell->params["NEG_CLK"] = "0";
new_cell->params["CARRY_ENABLE"] = "0";
new_cell->params["DFF_ENABLE"] = "0";
new_cell->params["SET_NORESET"] = "0";
new_cell->params["ASYNC_SR"] = "0";
add_port(new_cell, "I0", PORT_IN);
add_port(new_cell, "I1", PORT_IN);
add_port(new_cell, "I2", PORT_IN);
add_port(new_cell, "I3", PORT_IN);
add_port(new_cell, "CIN", PORT_IN);
add_port(new_cell, "CLK", PORT_IN);
add_port(new_cell, "CEN", PORT_IN);
add_port(new_cell, "SR", PORT_IN);
add_port(new_cell, "LO", PORT_OUT);
add_port(new_cell, "O", PORT_OUT);
add_port(new_cell, "OUT", PORT_OUT);
} else {
log_error("unable to create iCE40 cell of type %s", type.c_str());
}
design->cells[new_cell->name] = new_cell;
return new_cell;
}
void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
{
lc->params["DFF_ENABLE"] = "1";
std::string config = std::string(dff->type).substr(6);
auto citer = config.begin();
replace_port(dff, "C", lc, "CLK");
if (citer != config.end() && *citer == 'N') {
lc->params["NEG_CLK"] = "1";
++citer;
} else {
lc->params["NEG_CLK"] = "0";
}
if (citer != config.end() && *citer == 'E') {
replace_port(dff, "E", lc, "CEN");
++citer;
}
if (citer != config.end()) {
if ((config.end() - citer) >= 2) {
assert(*(citer++) == 'S');
lc->params["ASYNC_SR"] = "1";
} else {
lc->params["ASYNC_SR"] = "0";
}
if (*citer == 'S') {
replace_port(dff, "S", lc, "SR");
lc->params["SET_NORESET"] = "1";
} else {
assert(*citer == 'R');
replace_port(dff, "R", lc, "SR");
lc->params["SET_NORESET"] = "0";
}
}
assert(citer == config.end());
if (pass_thru_lut) {
lc->params["LUT_INIT"] = "2";
replace_port(dff, "D", lc, "I0");
}
}

54
ice40/cells.h Normal file
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@ -0,0 +1,54 @@
/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2018 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "nextpnr.h"
#ifndef ICE40_CELLS_H
#define ICE40_CELLS_H
// Create a standard iCE40 cell and return it
// Name will be automatically assigned if not specified
CellInfo *create_ice_cell(Design *design, IdString type,
IdString name = IdString());
// Return true if a cell is a LUT
inline bool is_lut(const CellInfo *cell) { return cell->type == "SB_LUT4"; }
// Return true if a cell is a flipflop
inline bool is_ff(const CellInfo *cell)
{
return cell->type == "SB_DFF" || cell->type == "SB_DFFE" ||
cell->type == "SB_DFFSR" || cell->type == "SB_DFFR" ||
cell->type == "SB_DFFSS" || cell->type == "SB_DFFS" ||
cell->type == "SB_DFFESR" || cell->type == "SB_DFFER" ||
cell->type == "SB_DFFESS" || cell->type == "SB_DFFES" ||
cell->type == "SB_DFFN" || cell->type == "SB_DFFNE" ||
cell->type == "SB_DFFNSR" || cell->type == "SB_DFFNR" ||
cell->type == "SB_DFFNSS" || cell->type == "SB_DFFNS" ||
cell->type == "SB_DFFNESR" || cell->type == "SB_DFFNER" ||
cell->type == "SB_DFFNESS" || cell->type == "SB_DFFNES";
}
// Convert a SB_DFFx primitive to (part of) an ICESTORM_LC, setting parameters
// and reconnecting signals as necessary. If pass_thru_lut is True, the LUT will
// be configured as pass through and D connected to I0, otherwise D will be
// ignored
void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut = false);
#endif