Merge pull request #619 from acomodi/add-cmake-infra-fpga-interchange
Add CMake infrastructure for fpga interchange
This commit is contained in:
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5feea4497f
48
.github/ci/build_interchange.sh
vendored
Executable file
48
.github/ci/build_interchange.sh
vendored
Executable file
@ -0,0 +1,48 @@
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#!/bin/bash
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# Install capnproto libraries
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curl -O https://capnproto.org/capnproto-c++-0.8.0.tar.gz
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tar zxf capnproto-c++-0.8.0.tar.gz
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pushd capnproto-c++-0.8.0
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./configure
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make -j`nproc` check
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sudo make install
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popd
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# Install latest Yosys
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git clone https://github.com/YosysHQ/yosys.git
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pushd yosys
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make -j`nproc`
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sudo make install
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popd
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# Install capnproto java
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git clone https://github.com/capnproto/capnproto-java.git
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pushd capnproto-java
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make
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sudo make install
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popd
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RAPIDWRIGHT_PATH="`pwd`/RapidWright"
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INTERCHANGE_SCHEMA_PATH="`pwd`/3rdparty/fpga-interchange-schema/interchange"
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PYTHON_INTERCHANGE_PATH="`pwd`/python-fpga-interchange"
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PYTHON_INTERCHANGE_TAG="v0.0.1"
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# Install python-fpga-interchange libraries
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git clone -b $PYTHON_INTERCHANGE_TAG https://github.com/SymbiFlow/python-fpga-interchange.git $PYTHON_INTERCHANGE_PATH
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pushd $PYTHON_INTERCHANGE_PATH
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git submodule update --init --recursive
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python3 -m pip install -r requirements.txt
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popd
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# Install RapidWright
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git clone https://github.com/Xilinx/RapidWright.git $RAPIDWRIGHT_PATH
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pushd $RAPIDWRIGHT_PATH
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make update_jars
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popd
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mkdir build
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pushd build
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cmake .. -DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=$RAPIDWRIGHT_PATH -DINTERCHANGE_SCHEMA_PATH=$INTERCHANGE_SCHEMA_PATH -DPYTHON_INTERCHANGE_PATH=$PYTHON_INTERCHANGE_PATH
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popd
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29
.github/workflows/interchange_ci.yml
vendored
Normal file
29
.github/workflows/interchange_ci.yml
vendored
Normal file
@ -0,0 +1,29 @@
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name: FPGA interchange CI tests
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on: [push, pull_request]
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jobs:
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Run-tests:
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v2
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with:
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submodules: recursive
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- uses: actions/setup-python@v2
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- name: Install
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run: |
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sudo apt-get update
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sudo apt-get install git make cmake libboost-all-dev python3-dev libeigen3-dev tcl-dev clang bison flex swig
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- name: Execute build script
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run: stdbuf -i0 -o0 -e0 ./.github/ci/build_interchange.sh
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- name: Run tests
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run: |
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cd build
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make all-fpga_interchange-archcheck-tests -j`nproc`
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make all-fpga_interchange-tests -j`nproc`
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2
3rdparty/fpga-interchange-schema
vendored
2
3rdparty/fpga-interchange-schema
vendored
@ -1 +1 @@
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Subproject commit bce42208b80c239d749881603b4cdf41944c70ad
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Subproject commit cb6d16847dfca7f104205c83bbdc056303ac82a0
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69
fpga_interchange/examples/README.md
Normal file
69
fpga_interchange/examples/README.md
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## FPGA interchange instructions
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These are instructions on how to get the dependencies, generate the FPGA interchange architecture build system and
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run some example designs.
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### Installing dependencies
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Install java and javac if not already installed:
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```
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# Or equivalent for your local system.
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sudo apt-get install openjdk-10-jdk
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```
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Install capnproto if not already installed. Version 0.8.0 is required.
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As stated in the [official instructions](https://capnproto.org/install.html), the version on the common package managers
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might not be up to date with the latest version, hence it is suggested to install
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from the archive or, in alternative, directly from the git repository.
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Install capnproto-java if not already installed:
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```
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git clone https://github.com/capnproto/capnproto-java.git
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cd capnproto-java
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make
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sudo make install
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```
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Install python-fpga-interchange if not already installed:
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```
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git clone https://github.com/SymbiFlow/python-fpga-interchange.git
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cd python-fpga-interchange.git
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python -m pip install -e .
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```
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Clone RapidWright, if not already cloned:
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```
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git clone https://github.com/Xilinx/RapidWright.git
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cd RapidWright
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make update_jars
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```
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### Build instructions
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Once dependencies are installed/cloned, configure the build system for the FPGA interchange.
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From the nextpnr root dir run:
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```
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mkdir build
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cd build
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cmake .. --DARCH=fpga_interchange -DRAPIDWRIGHT_PATH=<RapidWright path> -DINTERCHANGE_SCHEMA_PATH=<fpga-interchange-schema path> -DPYTHON_INTERCHANGE_PATH=<python-fpga-interchange path>
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```
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To build the xc7a35t architecture, run:
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```
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make chipdb-xc7a35t-bin
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```
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To build the example designs run:
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```
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make test-fpga_interchange-wire_arty-dcp
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```
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The make targets for the example designs follow the same pattern: `test-fpga_interchange-<test_name>-<output>`, where `output` is the name of the intermediate step of the build which can be:
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- `json`: synthesis output
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- `netlist`: logical netlist
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- `phys`: physical netlist
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- `dcp`: design checkpoint
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@ -1,23 +0,0 @@
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include ../common.mk
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PACKAGE := csg324
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.PHONY: check check_test_data
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check: check_test_data
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$(NEXTPNR_BIN) \
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--chipdb $(BBA_PATH) \
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--package $(PACKAGE) \
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--test
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check_test_data:
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$(NEXTPNR_BIN) \
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--chipdb $(BBA_PATH) \
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--package $(PACKAGE) \
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--run $(NEXTPNR_PATH)/python/check_arch_api.py
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debug_check_test_data:
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gdb --args $(NEXTPNR_BIN) \
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--chipdb $(BBA_PATH) \
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--package $(PACKAGE) \
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--run $(NEXTPNR_PATH)/python/check_arch_api.py
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334
fpga_interchange/examples/chipdb.cmake
Normal file
334
fpga_interchange/examples/chipdb.cmake
Normal file
@ -0,0 +1,334 @@
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function(create_rapidwright_device_db)
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# ~~~
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# create_rapidwright_device_db(
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# device <common device>
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# part <part>
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# output_target <output device target>
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# )
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# ~~~
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#
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# Generates a device database from RapidWright
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#
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# If output_target is specified, the output_target_name variable
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# is set to the generated output_device_file target.
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#
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# Arguments:
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# - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
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# share the same xc7a35t device prefix
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# - part: one among the parts available for a given device
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# - output_target: variable name that will hold the output device target for the parent scope
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#
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# Targets generated:
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# - rapidwright-<device>-device
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set(options)
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set(oneValueArgs device part output_target)
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set(multiValueArgs)
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cmake_parse_arguments(
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create_rapidwright_device_db
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"${options}"
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"${oneValueArgs}"
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"${multiValueArgs}"
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${ARGN}
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)
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set(device ${create_rapidwright_device_db_device})
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set(part ${create_rapidwright_device_db_part})
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set(output_target ${create_rapidwright_device_db_output_target})
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set(rapidwright_device_db ${CMAKE_CURRENT_BINARY_DIR}/${part}.device)
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add_custom_command(
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OUTPUT ${rapidwright_device_db}
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COMMAND
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RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
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${INVOKE_RAPIDWRIGHT}
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com.xilinx.rapidwright.interchange.DeviceResourcesExample
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${part}
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DEPENDS
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${INVOKE_RAPIDWRIGHT}
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)
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add_custom_target(rapidwright-${device}-device DEPENDS ${rapidwright_device_db})
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set_property(TARGET rapidwright-${device}-device PROPERTY LOCATION ${rapidwright_device_db})
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if (DEFINED output_target)
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set(${output_target} rapidwright-${device}-device PARENT_SCOPE)
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endif()
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endfunction()
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function(create_patched_device_db)
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# ~~~
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# create_patched_device_db(
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# device <common device>
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# patch_name <patch_name>
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# patch_path <patch_path>
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# patch_format <patch_format>
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# patch_data <patch_data>
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# input_device <input device target>
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# output_target <output device target>
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# )
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# ~~~
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#
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# Generates a patched device database starting from an input device
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#
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# If output_target is specified, the variable named as the output_target
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# parameter value is set to the generated output_device_file target.
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#
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# Arguments:
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# - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
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# share the same xc7a35t device prefix.
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# - patch_name: name of the patch which determines the target name
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# - patch_path: patch_path argument for the fpga_interchange.patch call
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# - patch_format: patch_format argument for the fpga_interchange.patch call
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# - patch_data: path to the patch_data required for the fpga_interchange.patch call
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# - input_device: target for the device that needs to be patched
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# - output_target: variable name that will hold the output device target for the parent scope
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#
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# Targets generated:
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# - <patch_name>-<device>-device
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set(options)
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set(oneValueArgs device patch_name patch_path patch_format patch_data input_device output_target)
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set(multiValueArgs)
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cmake_parse_arguments(
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create_patched_device_db
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"${options}"
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"${oneValueArgs}"
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"${multiValueArgs}"
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${ARGN}
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)
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set(device ${create_patched_device_db_device})
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set(patch_name ${create_patched_device_db_patch_name})
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set(patch_path ${create_patched_device_db_patch_path})
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set(patch_format ${create_patched_device_db_patch_format})
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set(patch_data ${create_patched_device_db_patch_data})
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set(input_device ${create_patched_device_db_input_device})
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set(output_target ${create_patched_device_db_output_target})
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get_target_property(input_device_loc ${input_device} LOCATION)
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set(output_device_file ${CMAKE_CURRENT_BINARY_DIR}/${device}_${patch_name}.device)
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add_custom_command(
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OUTPUT ${output_device_file}
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COMMAND
|
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${PYTHON_EXECUTABLE} -mfpga_interchange.patch
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--schema_dir ${INTERCHANGE_SCHEMA_PATH}
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--schema device
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--patch_path ${patch_path}
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--patch_format ${patch_format}
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${input_device_loc}
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${patch_data}
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${output_device_file}
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DEPENDS
|
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${patch_data}
|
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${input_device}
|
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${input_device_loc}
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)
|
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add_custom_target(${patch_name}-${device}-device DEPENDS ${output_device_file})
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set_property(TARGET ${patch_name}-${device}-device PROPERTY LOCATION ${output_device_file})
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|
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if (DEFINED output_target)
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set(${output_target} ${patch_name}-${device}-device PARENT_SCOPE)
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endif()
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endfunction()
|
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function(generate_xc7_device_db)
|
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# ~~~
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# generate_xc7_device_db(
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# device <common device>
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# part <part>
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||||
# device_target <variable name for device target>
|
||||
# )
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||||
# ~~~
|
||||
#
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# Generates a chipdb BBA file, starting from a RapidWright device database which is then patched.
|
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# Patches applied:
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||||
# - constraints patch
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# - luts patch
|
||||
#
|
||||
# Arguments:
|
||||
# - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
|
||||
# share the same xc7a35t device prefix
|
||||
# - part: one among the parts available for a given device
|
||||
# - device_target: variable name that will hold the output device target for the parent scope
|
||||
|
||||
set(options)
|
||||
set(oneValueArgs device part device_target)
|
||||
set(multiValueArgs)
|
||||
|
||||
cmake_parse_arguments(
|
||||
create_rapidwright_device_db
|
||||
"${options}"
|
||||
"${oneValueArgs}"
|
||||
"${multiValueArgs}"
|
||||
${ARGN}
|
||||
)
|
||||
|
||||
set(device ${create_rapidwright_device_db_device})
|
||||
set(part ${create_rapidwright_device_db_part})
|
||||
set(device_target ${create_rapidwright_device_db_device_target})
|
||||
|
||||
create_rapidwright_device_db(
|
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device ${device}
|
||||
part ${part}
|
||||
output_target rapidwright_device
|
||||
)
|
||||
|
||||
# Generate constraints patch
|
||||
create_patched_device_db(
|
||||
device ${device}
|
||||
patch_name constraints
|
||||
patch_path constraints
|
||||
patch_format yaml
|
||||
patch_data ${PYTHON_INTERCHANGE_PATH}/test_data/series7_constraints.yaml
|
||||
input_device ${rapidwright_device}
|
||||
output_target constraints_device
|
||||
)
|
||||
|
||||
# Generate lut constraints patch
|
||||
create_patched_device_db(
|
||||
device ${device}
|
||||
patch_name constraints-luts
|
||||
patch_path lutDefinitions
|
||||
patch_format yaml
|
||||
patch_data ${PYTHON_INTERCHANGE_PATH}/test_data/series7_luts.yaml
|
||||
input_device ${constraints_device}
|
||||
output_target constraints_luts_device
|
||||
)
|
||||
|
||||
if(DEFINED device_target)
|
||||
set(${device_target} ${constraints_luts_device} PARENT_SCOPE)
|
||||
endif()
|
||||
endfunction()
|
||||
|
||||
function(generate_chipdb)
|
||||
# ~~~
|
||||
# generate_chipdb(
|
||||
# family <family>
|
||||
# device <common device>
|
||||
# part <part>
|
||||
# device_target <device target>
|
||||
# bel_bucket_seeds <bel bucket seeds>
|
||||
# test_package <test_package>
|
||||
# )
|
||||
# ~~~
|
||||
#
|
||||
# Generates a chipdb BBA file, starting from a device database.
|
||||
#
|
||||
# The chipdb binary file is directly generated to the
|
||||
# <nextpnr-root>/build/fpga_interchange/chipdb/ directory.
|
||||
#
|
||||
# The package argument is only used to run the architecture check target.
|
||||
#
|
||||
# Arguments:
|
||||
# - family: nextpnr architecture family (e.g. fpga_interchange)
|
||||
# - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
|
||||
# share the same xc7a35t device prefix
|
||||
# - part: one among the parts available for a given device
|
||||
# - device_target: target for the device from which the chipdb is generated
|
||||
# - bel_bucket_seeds: path to the bel bucket seeds YAML file
|
||||
# - test_package: package among the ones available for the device. This is used for architecture
|
||||
# testing only
|
||||
#
|
||||
# Targets generated:
|
||||
# - chipdb-${device}-bba
|
||||
# - chipdb-${device}-bin
|
||||
# - device-${device}
|
||||
#
|
||||
# The device-${device} target contains properties to get the interchange device as well
|
||||
# as the binary chipdb
|
||||
|
||||
set(options)
|
||||
set(oneValueArgs family device part device_target bel_bucket_seeds test_package)
|
||||
set(multiValueArgs)
|
||||
|
||||
cmake_parse_arguments(
|
||||
generate_chipdb
|
||||
"${options}"
|
||||
"${oneValueArgs}"
|
||||
"${multiValueArgs}"
|
||||
${ARGN}
|
||||
)
|
||||
|
||||
set(family ${generate_chipdb_family})
|
||||
set(device ${generate_chipdb_device})
|
||||
set(part ${generate_chipdb_part})
|
||||
set(device_target ${generate_chipdb_device_target})
|
||||
set(bel_bucket_seeds ${generate_chipdb_bel_bucket_seeds})
|
||||
set(test_package ${generate_chipdb_test_package})
|
||||
|
||||
get_target_property(device_loc ${device_target} LOCATION)
|
||||
set(chipdb_bba ${CMAKE_CURRENT_BINARY_DIR}/chipdb.bba)
|
||||
add_custom_command(
|
||||
OUTPUT ${chipdb_bba}
|
||||
COMMAND
|
||||
${PYTHON_EXECUTABLE} -mfpga_interchange.nextpnr_emit
|
||||
--schema_dir ${INTERCHANGE_SCHEMA_PATH}
|
||||
--output_dir ${CMAKE_CURRENT_BINARY_DIR}
|
||||
--bel_bucket_seeds ${bel_bucket_seeds}
|
||||
--device ${device_loc}
|
||||
DEPENDS
|
||||
${bel_bucket_seeds}
|
||||
${device_target}
|
||||
${device_loc}
|
||||
)
|
||||
|
||||
add_custom_target(chipdb-${device}-bba DEPENDS ${chipdb_bba})
|
||||
|
||||
set(chipdb_bin ${chipdb_dir}/chipdb-${device}.bin)
|
||||
add_custom_command(
|
||||
OUTPUT ${chipdb_bin}
|
||||
COMMAND
|
||||
bbasm -l ${chipdb_bba} ${chipdb_bin}
|
||||
DEPENDS
|
||||
chipdb-${device}-bba
|
||||
${chipdb_bba}
|
||||
bbasm
|
||||
)
|
||||
|
||||
add_custom_target(chipdb-${device}-bin DEPENDS ${chipdb_bin})
|
||||
|
||||
# Setting device target properties
|
||||
add_custom_target(device-${device})
|
||||
set_target_properties(
|
||||
device-${device}
|
||||
PROPERTIES
|
||||
DEVICE_LOC ${device_loc}
|
||||
DEVICE_TARGET ${device_target}
|
||||
CHIPDB_BIN_LOC ${chipdb_bin}
|
||||
CHIPDB_BIN_TARGET chipdb-${device}-bin
|
||||
)
|
||||
|
||||
# Generate architecture check target
|
||||
add_custom_target(
|
||||
chipdb-${device}-bin-check
|
||||
COMMAND
|
||||
nextpnr-fpga_interchange
|
||||
--chipdb ${chipdb_bin}
|
||||
--package ${test_package}
|
||||
--test
|
||||
DEPENDS
|
||||
${chipdb_bin}
|
||||
chipdb-${device}-bin
|
||||
)
|
||||
|
||||
add_custom_target(
|
||||
chipdb-${device}-bin-check-test-data
|
||||
COMMAND
|
||||
nextpnr-fpga_interchange
|
||||
--chipdb ${chipdb_bin}
|
||||
--package ${test_package}
|
||||
--run ${PROJECT_SOURCE_DIR}/python/check_arch_api.py
|
||||
DEPENDS
|
||||
${chipdb_bin}
|
||||
chipdb-${device}-bin
|
||||
${test_data_binary}
|
||||
WORKING_DIRECTORY
|
||||
${CMAKE_CURRENT_SOURCE_DIR}
|
||||
)
|
||||
|
||||
add_dependencies(all-${family}-archcheck-tests chipdb-${device}-bin-check-test-data chipdb-${device}-bin-check)
|
||||
endfunction()
|
||||
|
||||
@ -1,8 +0,0 @@
|
||||
DESIGN := wire
|
||||
DESIGN_TOP := top
|
||||
PACKAGE := csg324
|
||||
|
||||
include ../template.mk
|
||||
|
||||
build/wire.json: wire.v | build
|
||||
yosys -c run.tcl
|
||||
@ -1,8 +0,0 @@
|
||||
DESIGN := counter
|
||||
DESIGN_TOP := top
|
||||
PACKAGE := cpg236
|
||||
|
||||
include ../template.mk
|
||||
|
||||
build/counter.json: counter.v | build
|
||||
yosys -c run.tcl
|
||||
@ -1,93 +0,0 @@
|
||||
#
|
||||
# nextpnr -- Next Generation Place and Route
|
||||
#
|
||||
# Copyright (C) 2021 Symbiflow Authors
|
||||
#
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for any
|
||||
# purpose with or without fee is hereby granted, provided that the above
|
||||
# copyright notice and this permission notice appear in all copies.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
|
||||
|
||||
# This Makefile provides a streamlined way to create an example
|
||||
# FPGA interchange BBA suitable for placing and routing on Xilinx A35 parts.
|
||||
#
|
||||
# FPGA interchange device database is generated via RapidWright.
|
||||
#
|
||||
# Currently FPGA interchange physical netlist (e.g. place and route route) to
|
||||
# FASM support is not done, so bitstream generation relies on RapidWright to
|
||||
# convert FPGA interchange logical and physical netlist into a Vivado DCP.
|
||||
|
||||
include ../common.mk
|
||||
|
||||
.DELETE_ON_ERROR:
|
||||
|
||||
.PHONY: all chipdb test debug_test
|
||||
|
||||
all: chipdb
|
||||
|
||||
build:
|
||||
mkdir build
|
||||
|
||||
build/RapidWright: | build
|
||||
cd build && git clone https://github.com/Xilinx/RapidWright.git
|
||||
|
||||
build/env: | build
|
||||
python3 -mvenv build/env
|
||||
|
||||
build/python-fpga-interchange: | build
|
||||
cd build && git clone https://github.com/SymbiFlow/python-fpga-interchange.git
|
||||
|
||||
build/fpga-interchange-schema: | build
|
||||
cd build && git clone https://github.com/SymbiFlow/fpga-interchange-schema.git
|
||||
|
||||
build/.setup: | build/env build/fpga-interchange-schema build/python-fpga-interchange build/RapidWright
|
||||
source build/env/bin/activate && \
|
||||
cd build/python-fpga-interchange/ && \
|
||||
pip install -r requirements.txt
|
||||
touch build/.setup
|
||||
|
||||
$(NEXTPNR_PATH)/build:
|
||||
mkdir $(NEXTPNR_PATH)/build
|
||||
|
||||
$(NEXTPNR_PATH)/build/bba/bbasm: | $(NEXTPNR_PATH)/build
|
||||
cd $(NEXTPNR_PATH)/build && cmake -DARCH=fpga_interchange ..
|
||||
make -j -C $(NEXTPNR_PATH)/build
|
||||
|
||||
build/nextpnr/fpga_interchange/chipdb.bba: build/.setup
|
||||
mkdir -p build/nextpnr/fpga_interchange
|
||||
source build/env/bin/activate && \
|
||||
cd build/python-fpga-interchange/ && \
|
||||
make \
|
||||
-f Makefile.rapidwright \
|
||||
NEXTPNR_PATH=$(realpath .)/build/nextpnr \
|
||||
RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
|
||||
INTERCHANGE_PATH=$(INTERCHANGE_PATH)
|
||||
|
||||
$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm build/nextpnr/fpga_interchange/chipdb.bba
|
||||
$(NEXTPNR_PATH)/build/bba/bbasm -l build/nextpnr/fpga_interchange/chipdb.bba $(BBA_PATH)
|
||||
|
||||
chipdb: $(BBA_PATH)
|
||||
|
||||
test: chipdb
|
||||
$(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
|
||||
--chipdb $(BBA_PATH) \
|
||||
--package csg324 \
|
||||
--test
|
||||
|
||||
debug_test: chipdb
|
||||
gdb --args $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
|
||||
--chipdb $(BBA_PATH) \
|
||||
--package csg324 \
|
||||
--test
|
||||
|
||||
clean:
|
||||
rm -rf build
|
||||
@ -1,40 +0,0 @@
|
||||
## Makefile-driven BBA creation
|
||||
|
||||
This Makefile will generate a Xilinx A35 chipdb if java, capnproto and
|
||||
capnproto-java are installed.
|
||||
|
||||
### Installing dependencies
|
||||
|
||||
Install java and javac if not already installed:
|
||||
```
|
||||
# Or equivalent for your local system.
|
||||
sudo apt-get install openjdk-10-jdk
|
||||
```
|
||||
|
||||
Install capnproto if not already installed:
|
||||
```
|
||||
# Or equivalent for your local system.
|
||||
sudo apt-get install capnproto libcapnp-dev
|
||||
```
|
||||
|
||||
Install capnproto-java if not already installed:
|
||||
```
|
||||
git clone https://github.com/capnproto/capnproto-java.git
|
||||
cd capnproto-java
|
||||
make
|
||||
sudo make install
|
||||
```
|
||||
|
||||
### Instructions
|
||||
|
||||
Once dependencies are installed, just run "make". This should download
|
||||
remaining dependencies and build the chipdb and build nextpnr if not built.
|
||||
|
||||
#### Re-building the chipdb
|
||||
|
||||
```
|
||||
# Remove the text BBA
|
||||
rm build/nextpnr/fpga_interchange/chipdb.bba
|
||||
# Build the BBA
|
||||
make
|
||||
```
|
||||
1
fpga_interchange/examples/devices/CMakeLists.txt
Normal file
1
fpga_interchange/examples/devices/CMakeLists.txt
Normal file
@ -0,0 +1 @@
|
||||
add_subdirectory(xc7a35t)
|
||||
14
fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
Normal file
14
fpga_interchange/examples/devices/xc7a35t/CMakeLists.txt
Normal file
@ -0,0 +1,14 @@
|
||||
generate_xc7_device_db(
|
||||
device xc7a35t
|
||||
part xc7a35tcsg324-1
|
||||
device_target xc7a35t_target
|
||||
)
|
||||
|
||||
generate_chipdb(
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
part xc7a35tcsg324-1
|
||||
device_target ${xc7a35t_target}
|
||||
bel_bucket_seeds ${PYTHON_INTERCHANGE_PATH}/test_data/series7_bel_buckets.yaml
|
||||
test_package csg324
|
||||
)
|
||||
@ -1,8 +0,0 @@
|
||||
DESIGN := ff
|
||||
DESIGN_TOP := top
|
||||
PACKAGE := csg324
|
||||
|
||||
include ../template.mk
|
||||
|
||||
build/ff.json: ff.v | build
|
||||
yosys -c run.tcl
|
||||
@ -1,8 +0,0 @@
|
||||
DESIGN := lut
|
||||
DESIGN_TOP := top
|
||||
PACKAGE := csg324
|
||||
|
||||
include ../template.mk
|
||||
|
||||
build/lut.json: lut.v | build
|
||||
yosys -c run.tcl
|
||||
179
fpga_interchange/examples/tests.cmake
Normal file
179
fpga_interchange/examples/tests.cmake
Normal file
@ -0,0 +1,179 @@
|
||||
function(add_interchange_test)
|
||||
# ~~~
|
||||
# add_interchange_test(
|
||||
# name <name>
|
||||
# family <family>
|
||||
# device <common device>
|
||||
# package <package>
|
||||
# tcl <tcl>
|
||||
# xdc <xdc>
|
||||
# sources <sources list>
|
||||
# [top <top name>]
|
||||
# [techmap <techmap file>]
|
||||
# )
|
||||
#
|
||||
# Generates targets to run desired tests
|
||||
#
|
||||
# Arguments:
|
||||
# - name: test name. This must be unique and no other tests with the same
|
||||
# name should exist
|
||||
# - family: nextpnr architecture family (e.g. fpga_interchange)
|
||||
# - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
|
||||
# share the same xc7a35t device prefix
|
||||
# - package: package among the ones available for the device
|
||||
# - tcl: tcl script used for synthesis
|
||||
# - xdc: constraints file used in the physical netlist generation step
|
||||
# - sources: list of HDL sources
|
||||
# - top (optional): name of the top level module.
|
||||
# If not provided, "top" is assigned as top level module
|
||||
# - techmap (optional): techmap file used during synthesis
|
||||
#
|
||||
# Targets generated:
|
||||
# - test-fpga_interchange-<name>-json : synthesis output
|
||||
# - test-fpga_interchange-<name>-netlist : interchange logical netlist
|
||||
# - test-fpga_interchange-<name>-phys : interchange physical netlist
|
||||
# - test-fpga_interchange-<name>-dcp : design checkpoint with RapidWright
|
||||
|
||||
set(options)
|
||||
set(oneValueArgs name family device package tcl xdc top techmap)
|
||||
set(multiValueArgs sources)
|
||||
|
||||
cmake_parse_arguments(
|
||||
add_interchange_test
|
||||
"${options}"
|
||||
"${oneValueArgs}"
|
||||
"${multiValueArgs}"
|
||||
${ARGN}
|
||||
)
|
||||
|
||||
set(name ${add_interchange_test_name})
|
||||
set(family ${add_interchange_test_family})
|
||||
set(device ${add_interchange_test_device})
|
||||
set(package ${add_interchange_test_package})
|
||||
set(top ${add_interchange_test_top})
|
||||
set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl})
|
||||
set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc})
|
||||
set(techmap ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_techmap})
|
||||
|
||||
set(sources)
|
||||
foreach(source ${add_interchange_test_sources})
|
||||
list(APPEND sources ${CMAKE_CURRENT_SOURCE_DIR}/${source})
|
||||
endforeach()
|
||||
|
||||
if (NOT DEFINED top)
|
||||
# Setting default top value
|
||||
set(top "top")
|
||||
endif()
|
||||
|
||||
# Synthesis
|
||||
set(synth_json ${CMAKE_CURRENT_BINARY_DIR}/${name}.json)
|
||||
add_custom_command(
|
||||
OUTPUT ${synth_json}
|
||||
COMMAND
|
||||
SOURCES=${sources}
|
||||
OUT_JSON=${synth_json}
|
||||
TECHMAP=${techmap}
|
||||
yosys -c ${tcl}
|
||||
DEPENDS ${sources}
|
||||
)
|
||||
|
||||
add_custom_target(test-${family}-${name}-json DEPENDS ${synth_json})
|
||||
|
||||
# Logical Netlist
|
||||
get_property(device_target TARGET device-${device} PROPERTY DEVICE_TARGET)
|
||||
get_property(device_loc TARGET device-${device} PROPERTY DEVICE_LOC)
|
||||
|
||||
set(netlist ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist)
|
||||
add_custom_command(
|
||||
OUTPUT ${netlist}
|
||||
COMMAND
|
||||
${PYTHON_EXECUTABLE} -mfpga_interchange.yosys_json
|
||||
--schema_dir ${INTERCHANGE_SCHEMA_PATH}
|
||||
--device ${device_loc}
|
||||
--top ${top}
|
||||
${synth_json}
|
||||
${netlist}
|
||||
DEPENDS
|
||||
${synth_json}
|
||||
${device_target}
|
||||
${device_loc}
|
||||
)
|
||||
|
||||
add_custom_target(test-${family}-${name}-netlist DEPENDS ${netlist})
|
||||
|
||||
# Logical Netlist YAML
|
||||
set(netlist_yaml ${CMAKE_CURRENT_BINARY_DIR}/${name}.netlist.yaml)
|
||||
add_custom_command(
|
||||
OUTPUT ${netlist_yaml}
|
||||
COMMAND
|
||||
${PYTHON_EXECUTABLE} -mfpga_interchange.convert
|
||||
--schema_dir ${INTERCHANGE_SCHEMA_PATH}
|
||||
--schema logical
|
||||
--input_format capnp
|
||||
--output_format yaml
|
||||
${netlist}
|
||||
${netlist_yaml}
|
||||
DEPENDS
|
||||
${netlist}
|
||||
)
|
||||
|
||||
add_custom_target(test-${family}-${name}-netlist-yaml DEPENDS ${netlist_yaml})
|
||||
|
||||
# Physical Netlist
|
||||
get_property(chipdb_bin_target TARGET device-${device} PROPERTY CHIPDB_BIN_TARGET)
|
||||
get_property(chipdb_bin_loc TARGET device-${device} PROPERTY CHIPDB_BIN_LOC)
|
||||
|
||||
set(phys ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys)
|
||||
add_custom_command(
|
||||
OUTPUT ${phys}
|
||||
COMMAND
|
||||
nextpnr-fpga_interchange
|
||||
--chipdb ${chipdb_bin_loc}
|
||||
--xdc ${xdc}
|
||||
--netlist ${netlist}
|
||||
--phys ${phys}
|
||||
--package ${package}
|
||||
DEPENDS
|
||||
${netlist}
|
||||
${xdc}
|
||||
${chipdb_bin_target}
|
||||
${chipdb_bin_loc}
|
||||
)
|
||||
|
||||
add_custom_target(test-${family}-${name}-phys DEPENDS ${phys})
|
||||
|
||||
# Physical Netlist YAML
|
||||
set(phys_yaml ${CMAKE_CURRENT_BINARY_DIR}/${name}.phys.yaml)
|
||||
add_custom_command(
|
||||
OUTPUT ${phys_yaml}
|
||||
COMMAND
|
||||
${PYTHON_EXECUTABLE} -mfpga_interchange.convert
|
||||
--schema_dir ${INTERCHANGE_SCHEMA_PATH}
|
||||
--schema physical
|
||||
--input_format capnp
|
||||
--output_format yaml
|
||||
${phys}
|
||||
${phys_yaml}
|
||||
DEPENDS
|
||||
${phys}
|
||||
)
|
||||
|
||||
add_custom_target(test-${family}-${name}-phys-yaml DEPENDS ${phys_yaml})
|
||||
|
||||
set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp)
|
||||
add_custom_command(
|
||||
OUTPUT ${dcp}
|
||||
COMMAND
|
||||
RAPIDWRIGHT_PATH=${RAPIDWRIGHT_PATH}
|
||||
${INVOKE_RAPIDWRIGHT}
|
||||
com.xilinx.rapidwright.interchange.PhysicalNetlistToDcp
|
||||
${netlist} ${phys} ${xdc} ${dcp}
|
||||
DEPENDS
|
||||
${INVOKE_RAPIDWRIGHT}
|
||||
${phys}
|
||||
${netlist}
|
||||
)
|
||||
|
||||
add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
|
||||
add_dependencies(all-${family}-tests test-${family}-${name}-dcp)
|
||||
endfunction()
|
||||
6
fpga_interchange/examples/tests/CMakeLists.txt
Normal file
6
fpga_interchange/examples/tests/CMakeLists.txt
Normal file
@ -0,0 +1,6 @@
|
||||
add_subdirectory(wire)
|
||||
add_subdirectory(const_wire)
|
||||
# FIXME: re-enable counter test as soon as post placement validity check completes successfully.
|
||||
#add_subdirectory(counter)
|
||||
add_subdirectory(ff)
|
||||
add_subdirectory(lut)
|
||||
19
fpga_interchange/examples/tests/const_wire/CMakeLists.txt
Normal file
19
fpga_interchange/examples/tests/const_wire/CMakeLists.txt
Normal file
@ -0,0 +1,19 @@
|
||||
add_interchange_test(
|
||||
name const_wire_basys3
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package cpg236
|
||||
tcl run.tcl
|
||||
xdc wire_basys3.xdc
|
||||
sources wire.v
|
||||
)
|
||||
|
||||
add_interchange_test(
|
||||
name const_wire_arty
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package csg324
|
||||
tcl run.tcl
|
||||
xdc wire_arty.xdc
|
||||
sources wire.v
|
||||
)
|
||||
@ -1,6 +1,6 @@
|
||||
yosys -import
|
||||
|
||||
read_verilog lut.v
|
||||
read_verilog $::env(SOURCES)
|
||||
|
||||
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
|
||||
|
||||
@ -11,4 +11,4 @@ opt_clean
|
||||
|
||||
setundef -zero -params
|
||||
|
||||
write_json build/lut.json
|
||||
write_json $::env(OUT_JSON)
|
||||
@ -0,0 +1,9 @@
|
||||
set_property PACKAGE_PIN U16 [get_ports o]
|
||||
set_property PACKAGE_PIN E19 [get_ports o2]
|
||||
set_property PACKAGE_PIN U19 [get_ports o3]
|
||||
set_property PACKAGE_PIN V19 [get_ports o4]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports o]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports o2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports o3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports o4]
|
||||
21
fpga_interchange/examples/tests/counter/CMakeLists.txt
Normal file
21
fpga_interchange/examples/tests/counter/CMakeLists.txt
Normal file
@ -0,0 +1,21 @@
|
||||
add_interchange_test(
|
||||
name counter_basys3
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package cpg236
|
||||
tcl run.tcl
|
||||
xdc counter_basys3.xdc
|
||||
sources counter.v
|
||||
techmap remap.v
|
||||
)
|
||||
|
||||
add_interchange_test(
|
||||
name counter_arty
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package csg324
|
||||
tcl run.tcl
|
||||
xdc counter_arty.xdc
|
||||
sources counter.v
|
||||
techmap remap.v
|
||||
)
|
||||
14
fpga_interchange/examples/tests/counter/counter_arty.xdc
Normal file
14
fpga_interchange/examples/tests/counter/counter_arty.xdc
Normal file
@ -0,0 +1,14 @@
|
||||
## basys3 breakout board
|
||||
set_property PACKAGE_PIN E3 [get_ports clk]
|
||||
set_property PACKAGE_PIN C2 [get_ports rst]
|
||||
set_property PACKAGE_PIN N15 [get_ports io_led[4]]
|
||||
set_property PACKAGE_PIN N16 [get_ports io_led[5]]
|
||||
set_property PACKAGE_PIN P17 [get_ports io_led[6]]
|
||||
set_property PACKAGE_PIN R17 [get_ports io_led[7]]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports rst]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
|
||||
@ -1,10 +1,6 @@
|
||||
## basys3 breakout board
|
||||
set_property PACKAGE_PIN W5 [get_ports clk]
|
||||
set_property PACKAGE_PIN V17 [get_ports rst]
|
||||
#set_property PACKAGE_PIN U16 [get_ports io_led[0]]
|
||||
#set_property PACKAGE_PIN E19 [get_ports io_led[1]]
|
||||
#set_property PACKAGE_PIN U19 [get_ports io_led[2]]
|
||||
#set_property PACKAGE_PIN V19 [get_ports io_led[3]]
|
||||
set_property PACKAGE_PIN U16 [get_ports io_led[4]]
|
||||
set_property PACKAGE_PIN E19 [get_ports io_led[5]]
|
||||
set_property PACKAGE_PIN U19 [get_ports io_led[6]]
|
||||
@ -16,7 +12,3 @@ set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports io_led[0]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports io_led[1]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports io_led[2]]
|
||||
#set_property IOSTANDARD LVCMOS33 [get_ports io_led[3]]
|
||||
11
fpga_interchange/examples/tests/counter/remap.v
Normal file
11
fpga_interchange/examples/tests/counter/remap.v
Normal file
@ -0,0 +1,11 @@
|
||||
module INV(input I, output O);
|
||||
|
||||
LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
|
||||
|
||||
endmodule
|
||||
|
||||
module BUF(input I, output O);
|
||||
|
||||
LUT1 #(.INIT(2'b10)) _TECHMAP_REPLACE_ (.I0(I), .O(O));
|
||||
|
||||
endmodule
|
||||
@ -1,9 +1,9 @@
|
||||
yosys -import
|
||||
|
||||
read_verilog counter.v
|
||||
read_verilog $::env(SOURCES)
|
||||
|
||||
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
|
||||
techmap -map ../remap.v
|
||||
techmap -map $::env(TECHMAP)
|
||||
|
||||
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
|
||||
# net.
|
||||
@ -12,4 +12,4 @@ opt_clean
|
||||
|
||||
setundef -zero -params
|
||||
|
||||
write_json build/counter.json
|
||||
write_json $::env(OUT_JSON)
|
||||
19
fpga_interchange/examples/tests/ff/CMakeLists.txt
Normal file
19
fpga_interchange/examples/tests/ff/CMakeLists.txt
Normal file
@ -0,0 +1,19 @@
|
||||
add_interchange_test(
|
||||
name ff_basys3
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package cpg236
|
||||
tcl run.tcl
|
||||
xdc ff_basys3.xdc
|
||||
sources ff.v
|
||||
)
|
||||
|
||||
add_interchange_test(
|
||||
name ff_arty
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package csg324
|
||||
tcl run.tcl
|
||||
xdc ff_arty.xdc
|
||||
sources ff.v
|
||||
)
|
||||
9
fpga_interchange/examples/tests/ff/ff_basys3.xdc
Normal file
9
fpga_interchange/examples/tests/ff/ff_basys3.xdc
Normal file
@ -0,0 +1,9 @@
|
||||
set_property PACKAGE_PIN W5 [get_ports clk]
|
||||
set_property PACKAGE_PIN U16 [get_ports d]
|
||||
set_property PACKAGE_PIN E19 [get_ports r]
|
||||
set_property PACKAGE_PIN U19 [get_ports q]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports d]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports r]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports q]
|
||||
@ -1,6 +1,6 @@
|
||||
yosys -import
|
||||
|
||||
read_verilog wire.v
|
||||
read_verilog $::env(SOURCES)
|
||||
|
||||
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
|
||||
|
||||
@ -11,4 +11,4 @@ opt_clean
|
||||
|
||||
setundef -zero -params
|
||||
|
||||
write_json build/wire.json
|
||||
write_json $::env(OUT_JSON)
|
||||
19
fpga_interchange/examples/tests/lut/CMakeLists.txt
Normal file
19
fpga_interchange/examples/tests/lut/CMakeLists.txt
Normal file
@ -0,0 +1,19 @@
|
||||
add_interchange_test(
|
||||
name lut_basys3
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package cpg236
|
||||
tcl run.tcl
|
||||
xdc lut_basys3.xdc
|
||||
sources lut.v
|
||||
)
|
||||
|
||||
add_interchange_test(
|
||||
name lut_arty
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package csg324
|
||||
tcl run.tcl
|
||||
xdc lut_arty.xdc
|
||||
sources lut.v
|
||||
)
|
||||
7
fpga_interchange/examples/tests/lut/lut_basys3.xdc
Normal file
7
fpga_interchange/examples/tests/lut/lut_basys3.xdc
Normal file
@ -0,0 +1,7 @@
|
||||
set_property PACKAGE_PIN V17 [get_ports i0]
|
||||
set_property PACKAGE_PIN V16 [get_ports i1]
|
||||
set_property PACKAGE_PIN U16 [get_ports o]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports i0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports i1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports o]
|
||||
@ -1,6 +1,6 @@
|
||||
yosys -import
|
||||
|
||||
read_verilog wire.v
|
||||
read_verilog $::env(SOURCES)
|
||||
|
||||
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
|
||||
|
||||
@ -11,4 +11,4 @@ opt_clean
|
||||
|
||||
setundef -zero -params
|
||||
|
||||
write_json build/wire.json
|
||||
write_json $::env(OUT_JSON)
|
||||
19
fpga_interchange/examples/tests/wire/CMakeLists.txt
Normal file
19
fpga_interchange/examples/tests/wire/CMakeLists.txt
Normal file
@ -0,0 +1,19 @@
|
||||
add_interchange_test(
|
||||
name wire_basys3
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package cpg236
|
||||
tcl run.tcl
|
||||
xdc wire_basys3.xdc
|
||||
sources wire.v
|
||||
)
|
||||
|
||||
add_interchange_test(
|
||||
name wire_arty
|
||||
family ${family}
|
||||
device xc7a35t
|
||||
package csg324
|
||||
tcl run.tcl
|
||||
xdc wire_arty.xdc
|
||||
sources wire.v
|
||||
)
|
||||
@ -1,6 +1,6 @@
|
||||
yosys -import
|
||||
|
||||
read_verilog ff.v
|
||||
read_verilog $::env(SOURCES)
|
||||
|
||||
synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
|
||||
|
||||
@ -11,4 +11,4 @@ opt_clean
|
||||
|
||||
setundef -zero -params
|
||||
|
||||
write_json build/ff.json
|
||||
write_json $::env(OUT_JSON)
|
||||
5
fpga_interchange/examples/tests/wire/wire_basys3.xdc
Normal file
5
fpga_interchange/examples/tests/wire/wire_basys3.xdc
Normal file
@ -0,0 +1,5 @@
|
||||
set_property PACKAGE_PIN V17 [get_ports i]
|
||||
set_property PACKAGE_PIN U16 [get_ports o]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports i]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports o]
|
||||
@ -1,8 +0,0 @@
|
||||
DESIGN := wire
|
||||
DESIGN_TOP := top
|
||||
PACKAGE := csg324
|
||||
|
||||
include ../template.mk
|
||||
|
||||
build/wire.json: wire.v | build
|
||||
yosys -c run.tcl
|
||||
@ -5,8 +5,25 @@ endif()
|
||||
|
||||
find_package(ZLIB REQUIRED)
|
||||
|
||||
set(RAPIDWRIGHT_PATH $ENV{HOME}/RapidWright CACHE PATH "Path to RapidWright")
|
||||
set(INVOKE_RAPIDWRIGHT ${RAPIDWRIGHT_PATH}/scripts/invoke_rapidwright.sh CACHE PATH "Path to RapidWright invocation script")
|
||||
# FIXME: Make patch data available in the python package and remove this cached var
|
||||
set(PYTHON_INTERCHANGE_PATH $ENV{HOME}/python-fpga-interchange CACHE PATH "Path to the FPGA interchange python library")
|
||||
set(INTERCHANGE_SCHEMA_PATH $ENV{HOME}/fpga_interchange_schema CACHE PATH "Path to the FPGA interchange schema dir")
|
||||
|
||||
add_subdirectory(3rdparty/fpga-interchange-schema/cmake/cxx_static)
|
||||
|
||||
include(${family}/examples/chipdb.cmake)
|
||||
include(${family}/examples/tests.cmake)
|
||||
|
||||
set(chipdb_dir ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb)
|
||||
file(MAKE_DIRECTORY ${chipdb_dir})
|
||||
|
||||
add_custom_target(all-${family}-tests)
|
||||
add_custom_target(all-${family}-archcheck-tests)
|
||||
add_subdirectory(${family}/examples/devices)
|
||||
add_subdirectory(${family}/examples/tests)
|
||||
|
||||
foreach (target ${family_targets})
|
||||
target_include_directories(${target} PRIVATE ${TCL_INCLUDE_PATH})
|
||||
target_link_libraries(${target} PRIVATE ${TCL_LIBRARY})
|
||||
|
||||
Loading…
Reference in New Issue
Block a user