Refactor Chip API and iCE40 database
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
d3f19cc27e
commit
5ff9aafb20
@ -21,6 +21,7 @@
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#define DESIGN_H
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#include <stdint.h>
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#include <assert.h>
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#include <vector>
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#include <string>
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#include <unordered_set>
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@ -36,11 +36,6 @@
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void arch_wrap_python();
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BOOST_PYTHON_MODULE (MODULE_NAME) {
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// From Chip.h
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WRAP_RANGE(Bel);
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WRAP_RANGE(WireDelay);
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WRAP_RANGE(BelPin);
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arch_wrap_python();
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}
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120
ice40/chip.cc
120
ice40/chip.cc
@ -278,10 +278,16 @@ PortPin PortPinFromId(IdString id)
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Chip::Chip(ChipArgs args)
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{
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if (args.type == ChipArgs::LP384) {
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num_bels = 0;
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bel_data = nullptr;
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num_wires = num_wires_384;
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wire_data = wire_data_384;
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chip_info = chip_info_384;
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return;
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} else if (args.type == ChipArgs::LP1K || args.type == ChipArgs::HX1K) {
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chip_info = chip_info_1k;
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return;
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} else if (args.type == ChipArgs::UP5K) {
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chip_info = chip_info_5k;
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return;
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} else if (args.type == ChipArgs::LP8K || args.type == ChipArgs::HX8K) {
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chip_info = chip_info_8k;
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return;
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} else {
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fprintf(stderr, "Unsupported chip type\n");
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@ -291,13 +297,15 @@ Chip::Chip(ChipArgs args)
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abort();
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}
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// -----------------------------------------------------------------------
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BelId Chip::getBelByName(IdString name) const
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{
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BelId ret;
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if (bel_by_name.empty()) {
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for (int i = 0; i < num_bels; i++)
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bel_by_name[bel_data[i].name] = i;
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for (int i = 0; i < chip_info.num_bels; i++)
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bel_by_name[chip_info.bel_data[i].name] = i;
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}
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auto it = bel_by_name.find(name);
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@ -307,24 +315,92 @@ BelId Chip::getBelByName(IdString name) const
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return ret;
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}
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WireId Chip::getWireByName(IdString name) const
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{
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WireId ret;
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if (wire_by_name.empty()) {
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for (int i = 0; i < num_wires; i++)
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wire_by_name[wire_data[i].name] = i;
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}
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auto it = wire_by_name.find(name);
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if (it != wire_by_name.end())
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ret.index = it->second;
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return ret;
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}
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WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
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{
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// FIXME
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return WireId();
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}
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// -----------------------------------------------------------------------
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WireId Chip::getWireByName(IdString name) const
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{
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WireId ret;
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if (wire_by_name.empty()) {
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for (int i = 0; i < chip_info.num_wires; i++)
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wire_by_name[chip_info.wire_data[i].name] = i;
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}
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auto it = wire_by_name.find(name);
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if (it != wire_by_name.end())
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ret.index = it->second;
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return ret;
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}
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// -----------------------------------------------------------------------
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PipId Chip::getPipByName(IdString name) const
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{
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PipId ret;
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if (pip_by_name.empty()) {
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for (int i = 0; i < chip_info.num_pips; i++) {
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PipId pip;
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pip.index = i;
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pip_by_name[getPipName(pip)] = i;
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}
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}
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auto it = pip_by_name.find(name);
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if (it != pip_by_name.end())
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ret.index = it->second;
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return ret;
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}
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// -----------------------------------------------------------------------
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void Chip::getBelPosition(BelId bel, float &x, float &y) const
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{
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// FIXME
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}
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void Chip::getWirePosition(WireId wire, float &x, float &y) const
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{
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// FIXME
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}
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void Chip::getPipPosition(WireId wire, float &x, float &y) const
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{
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// FIXME
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}
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vector<GraphicElement> Chip::getBelGraphics(BelId bel) const
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{
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vector<GraphicElement> ret;
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// FIXME
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return ret;
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}
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vector<GraphicElement> Chip::getWireGraphics(WireId wire) const
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{
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vector<GraphicElement> ret;
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// FIXME
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return ret;
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}
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vector<GraphicElement> Chip::getPipGraphics(PipId pip) const
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{
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vector<GraphicElement> ret;
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// FIXME
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return ret;
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}
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vector<GraphicElement> Chip::getFrameGraphics() const
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{
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vector<GraphicElement> ret;
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// FIXME
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return ret;
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}
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406
ice40/chip.h
406
ice40/chip.h
@ -166,48 +166,41 @@ struct BelInfoPOD
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BelType type;
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};
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struct WireDelayPOD
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{
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int32_t wire_index;
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float delay;
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};
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struct BelPortPOD
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{
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int32_t bel_index;
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PortPin port;
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};
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struct PipInfoPOD
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{
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int32_t src, dst;
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float delay;
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};
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struct WireInfoPOD
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{
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const char *name;
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int num_uphill, num_downhill, num_bidir;
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WireDelayPOD *wires_uphill, *wires_downhill, *wires_bidir;
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int num_uphill, num_downhill;
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int *pips_uphill, *pips_downhill;
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int num_bels_downhill;
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BelPortPOD bel_uphill;
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BelPortPOD *bels_downhill;
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};
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extern int num_bels_384;
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extern int num_bels_1k;
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extern int num_bels_5k;
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extern int num_bels_8k;
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struct ChipInfoPOD
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{
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int num_bels, num_wires, num_pips;
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BelInfoPOD *bel_data;
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WireInfoPOD *wire_data;
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PipInfoPOD *pip_data;
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};
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extern BelInfoPOD bel_data_384[];
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extern BelInfoPOD bel_data_1k[];
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extern BelInfoPOD bel_data_5k[];
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extern BelInfoPOD bel_data_8k[];
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extern int num_wires_384;
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extern int num_wires_1k;
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extern int num_wires_5k;
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extern int num_wires_8k;
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extern WireInfoPOD wire_data_384[];
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extern WireInfoPOD wire_data_1k[];
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extern WireInfoPOD wire_data_5k[];
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extern WireInfoPOD wire_data_8k[];
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extern ChipInfoPOD chip_info_384;
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extern ChipInfoPOD chip_info_1k;
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extern ChipInfoPOD chip_info_5k;
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extern ChipInfoPOD chip_info_8k;
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// -----------------------------------------------------------------------
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@ -229,6 +222,21 @@ struct WireId
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}
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};
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struct PipId
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{
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int32_t index = -1;
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bool nil() const {
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return index < 0;
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}
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};
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struct BelPin
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{
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BelId bel;
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PortPin pin;
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};
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namespace std
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{
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template<> struct hash<BelId>
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@ -246,6 +254,14 @@ namespace std
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return wire.index;
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}
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};
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template<> struct hash<PipId>
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{
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std::size_t operator()(const PipId &wire) const noexcept
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{
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return wire.index;
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}
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};
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}
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// -----------------------------------------------------------------------
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@ -273,65 +289,6 @@ struct BelRange
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// -----------------------------------------------------------------------
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struct AllWireIterator
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{
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int cursor;
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void operator++() { cursor++; }
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bool operator!=(const AllWireIterator &other) const { return cursor != other.cursor; }
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WireId operator*() const {
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WireId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct AllWireRange
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{
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AllWireIterator b, e;
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AllWireIterator begin() const { return b; }
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AllWireIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct WireDelay
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{
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WireId wire;
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DelayInfo delay;
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};
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struct WireDelayIterator
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{
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WireDelayPOD *ptr = nullptr;
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void operator++() { ptr++; }
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bool operator!=(const WireDelayIterator &other) const { return ptr != other.ptr; }
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WireDelay operator*() const {
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WireDelay ret;
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ret.wire.index = ptr->wire_index;
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ret.delay.delay = ptr->delay;
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return ret;
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}
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};
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struct WireDelayRange
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{
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WireDelayIterator b, e;
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WireDelayIterator begin() const { return b; }
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WireDelayIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct BelPin
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{
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BelId bel;
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PortPin pin;
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};
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struct BelPinIterator
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{
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BelPortPOD *ptr = nullptr;
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@ -356,6 +313,75 @@ struct BelPinRange
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// -----------------------------------------------------------------------
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struct WireIterator
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{
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int cursor = -1;
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void operator++() { cursor++; }
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bool operator!=(const WireIterator &other) const { return cursor != other.cursor; }
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WireId operator*() const {
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WireId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct WireRange
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{
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WireIterator b, e;
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WireIterator begin() const { return b; }
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WireIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct AllPipIterator
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{
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int cursor = -1;
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void operator++() { cursor++; }
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bool operator!=(const AllPipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const {
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PipId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct AllPipRange
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{
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AllPipIterator b, e;
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AllPipIterator begin() const { return b; }
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AllPipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct PipIterator
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{
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int *cursor = nullptr;
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void operator++() { cursor++; }
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bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const {
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PipId ret;
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ret.index = *cursor;
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return ret;
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}
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};
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struct PipRange
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{
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PipIterator b, e;
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PipIterator begin() const { return b; }
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PipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct ChipArgs
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{
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enum {
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@ -371,36 +397,41 @@ struct ChipArgs
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struct Chip
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{
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int num_bels, num_wires;
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BelInfoPOD *bel_data;
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WireInfoPOD *wire_data;
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ChipInfoPOD chip_info;
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mutable dict<IdString, int> wire_by_name;
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mutable dict<IdString, int> bel_by_name;
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mutable dict<IdString, int> wire_by_name;
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mutable dict<IdString, int> pip_by_name;
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Chip(ChipArgs args);
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void setBelActive(BelId, bool) { }
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bool getBelActive(BelId) { return true; }
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// -------------------------------------------------
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BelId getBelByName(IdString name) const;
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WireId getWireByName(IdString name) const;
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IdString getBelName(BelId bel) const
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{
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return bel_data[bel.index].name;
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assert(!bel.nil());
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return chip_info.bel_data[bel.index].name;
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}
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IdString getWireName(WireId wire) const
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void bindBel(BelId bel, IdString cell)
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{
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}
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void unbindBel(BelId bel)
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{
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}
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bool checkBelAvail(BelId bel) const
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{
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return wire_data[wire.index].name;
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}
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BelRange getBels() const
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{
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BelRange range;
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range.b.cursor = 0;
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range.e.cursor = num_bels;
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range.e.cursor = chip_info.num_bels;
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return range;
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}
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@ -420,52 +451,8 @@ struct Chip
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BelType getBelType(BelId bel) const
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{
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return bel_data[bel.index].type;
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}
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// FIXME: void getBelPosition(BelId bel, float &x, float &y) const;
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// FIXME: void getWirePosition(WireId wire, float &x, float &y) const;
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// FIXME: vector<GraphicElement> getBelGraphics(BelId bel) const;
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// FIXME: vector<GraphicElement> getWireGraphics(WireId wire) const;
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// FIXME: vector<GraphicElement> getPipGraphics(WireId src, WireId dst) const;
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// FIXME: vector<GraphicElement> getFrameGraphics() const;
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AllWireRange getWires() const
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{
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AllWireRange range;
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range.b.cursor = 0;
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range.e.cursor = num_wires;
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return range;
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}
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WireDelayRange getWiresUphill(WireId wire) const
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{
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WireDelayRange range;
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range.b.ptr = wire_data[wire.index].wires_uphill;
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range.e.ptr = wire_data[wire.index].wires_uphill + wire_data[wire.index].num_uphill;
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return range;
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}
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WireDelayRange getWiresDownhill(WireId wire) const
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{
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WireDelayRange range;
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range.b.ptr = wire_data[wire.index].wires_downhill;
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range.e.ptr = wire_data[wire.index].wires_downhill + wire_data[wire.index].num_downhill;
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return range;
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}
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WireDelayRange getWiresBidir(WireId wire) const
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{
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WireDelayRange range;
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range.b.ptr = wire_data[wire.index].wires_bidir;
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range.e.ptr = wire_data[wire.index].wires_bidir + wire_data[wire.index].num_bidir;
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return range;
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}
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WireDelayRange getWireAliases(WireId wire) const
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{
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WireDelayRange range;
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return range;
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assert(!bel.nil());
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return chip_info.bel_data[bel.index].type;
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}
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WireId getWireBelPin(BelId bel, PortPin pin) const;
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@ -473,10 +460,11 @@ struct Chip
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BelPin getBelPinUphill(WireId wire) const
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{
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BelPin ret;
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assert(!wire.nil());
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if (wire_data[wire.index].bel_uphill.bel_index >= 0) {
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ret.bel.index = wire_data[wire.index].bel_uphill.bel_index;
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ret.pin = wire_data[wire.index].bel_uphill.port;
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if (chip_info.wire_data[wire.index].bel_uphill.bel_index >= 0) {
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ret.bel.index = chip_info.wire_data[wire.index].bel_uphill.bel_index;
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ret.pin = chip_info.wire_data[wire.index].bel_uphill.port;
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}
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return ret;
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@ -485,10 +473,134 @@ struct Chip
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BelPinRange getBelPinsDownhill(WireId wire) const
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{
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BelPinRange range;
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range.b.ptr = wire_data[wire.index].bels_downhill;
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range.e.ptr = wire_data[wire.index].bels_downhill + wire_data[wire.index].num_bels_downhill;
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assert(!wire.nil());
|
||||
range.b.ptr = chip_info.wire_data[wire.index].bels_downhill;
|
||||
range.e.ptr = range.b.ptr + chip_info.wire_data[wire.index].num_bels_downhill;
|
||||
return range;
|
||||
}
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
WireId getWireByName(IdString name) const;
|
||||
|
||||
IdString getWireName(WireId wire) const
|
||||
{
|
||||
assert(!wire.nil());
|
||||
return chip_info.wire_data[wire.index].name;
|
||||
}
|
||||
|
||||
void bindWire(WireId bel, IdString net)
|
||||
{
|
||||
}
|
||||
|
||||
void unbindWire(WireId bel)
|
||||
{
|
||||
}
|
||||
|
||||
bool checkWireAvail(WireId bel) const
|
||||
{
|
||||
}
|
||||
|
||||
WireRange getWires() const
|
||||
{
|
||||
WireRange range;
|
||||
range.b.cursor = 0;
|
||||
range.e.cursor = chip_info.num_wires;
|
||||
return range;
|
||||
}
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
PipId getPipByName(IdString name) const;
|
||||
|
||||
IdString getPipName(PipId pip) const
|
||||
{
|
||||
assert(!pip.nil());
|
||||
std::string src_name = chip_info.wire_data[chip_info.pip_data[pip.index].src].name;
|
||||
std::string dst_name = chip_info.wire_data[chip_info.pip_data[pip.index].dst].name;
|
||||
return src_name + "->" + dst_name;
|
||||
}
|
||||
|
||||
void bindPip(PipId bel, IdString net)
|
||||
{
|
||||
}
|
||||
|
||||
void unbindPip(PipId bel)
|
||||
{
|
||||
}
|
||||
|
||||
bool checkPipAvail(PipId bel) const
|
||||
{
|
||||
}
|
||||
|
||||
AllPipRange getPips() const
|
||||
{
|
||||
AllPipRange range;
|
||||
range.b.cursor = 0;
|
||||
range.e.cursor = chip_info.num_pips;
|
||||
return range;
|
||||
}
|
||||
|
||||
WireId getPipSrcWire(PipId pip) const
|
||||
{
|
||||
WireId wire;
|
||||
assert(!pip.nil());
|
||||
wire.index = chip_info.pip_data[pip.index].src;
|
||||
return wire;
|
||||
}
|
||||
|
||||
WireId getPipDstWire(PipId pip) const
|
||||
{
|
||||
WireId wire;
|
||||
assert(!pip.nil());
|
||||
wire.index = chip_info.pip_data[pip.index].dst;
|
||||
return wire;
|
||||
}
|
||||
|
||||
DelayInfo getPipDelay(PipId pip) const
|
||||
{
|
||||
DelayInfo delay;
|
||||
assert(!pip.nil());
|
||||
delay.delay = chip_info.pip_data[pip.index].delay;
|
||||
return delay;
|
||||
}
|
||||
|
||||
PipRange getPipsDownhill(WireId wire) const
|
||||
{
|
||||
PipRange range;
|
||||
assert(!wire.nil());
|
||||
range.b.cursor = chip_info.wire_data[wire.index].pips_downhill;
|
||||
range.e.cursor = range.b.cursor + chip_info.wire_data[wire.index].num_downhill;
|
||||
return range;
|
||||
}
|
||||
|
||||
PipRange getPipsUphill(WireId wire) const
|
||||
{
|
||||
PipRange range;
|
||||
assert(!wire.nil());
|
||||
range.b.cursor = chip_info.wire_data[wire.index].pips_uphill;
|
||||
range.e.cursor = range.b.cursor + chip_info.wire_data[wire.index].num_uphill;
|
||||
return range;
|
||||
}
|
||||
|
||||
PipRange getWireAliases(WireId wire) const
|
||||
{
|
||||
PipRange range;
|
||||
assert(!wire.nil());
|
||||
range.b.cursor = nullptr;
|
||||
range.e.cursor = nullptr;
|
||||
return range;
|
||||
}
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
void getBelPosition(BelId bel, float &x, float &y) const;
|
||||
void getWirePosition(WireId wire, float &x, float &y) const;
|
||||
void getPipPosition(WireId wire, float &x, float &y) const;
|
||||
vector<GraphicElement> getBelGraphics(BelId bel) const;
|
||||
vector<GraphicElement> getWireGraphics(WireId wire) const;
|
||||
vector<GraphicElement> getPipGraphics(PipId pip) const;
|
||||
vector<GraphicElement> getFrameGraphics() const;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@ -11,7 +11,6 @@ tiles = dict()
|
||||
|
||||
wire_uphill = dict()
|
||||
wire_downhill = dict()
|
||||
wire_bidir = dict()
|
||||
|
||||
bel_name = list()
|
||||
bel_type = list()
|
||||
@ -98,12 +97,20 @@ with open(sys.argv[1], "r") as f:
|
||||
if mode[0] == "routing":
|
||||
wire_a = int(line[1])
|
||||
wire_b = mode[1]
|
||||
if wire_a not in wire_bidir:
|
||||
wire_bidir[wire_a] = set()
|
||||
if wire_b not in wire_bidir:
|
||||
wire_bidir[wire_b] = set()
|
||||
wire_bidir[wire_a].add(wire_b)
|
||||
wire_bidir[wire_b].add(wire_b)
|
||||
|
||||
if wire_a not in wire_downhill:
|
||||
wire_downhill[wire_a] = set()
|
||||
if wire_b not in wire_uphill:
|
||||
wire_uphill[wire_b] = set()
|
||||
wire_downhill[wire_a].add(wire_b)
|
||||
wire_uphill[wire_b].add(wire_a)
|
||||
|
||||
if wire_b not in wire_downhill:
|
||||
wire_downhill[wire_b] = set()
|
||||
if wire_a not in wire_uphill:
|
||||
wire_uphill[wire_a] = set()
|
||||
wire_downhill[wire_b].add(wire_a)
|
||||
wire_uphill[wire_a].add(wire_b)
|
||||
continue
|
||||
|
||||
def add_bel_input(bel, wire, port):
|
||||
@ -222,51 +229,55 @@ for tile_xy, tile_type in sorted(tiles.items()):
|
||||
|
||||
print('#include "chip.h"')
|
||||
|
||||
print("int num_bels_%s = %d;" % (dev_name, num_wires))
|
||||
print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, num_wires))
|
||||
print("BelInfoPOD bel_data_%s[%d] = {" % (dev_name, len(bel_name)))
|
||||
for bel in range(len(bel_name)):
|
||||
print(" {\"%s\", TYPE_%s}%s" % (bel_name[bel], bel_type[bel], "," if bel+1 < len(bel_name) else ""))
|
||||
print("};")
|
||||
|
||||
wireinfo = list()
|
||||
pipinfo = list()
|
||||
pipcache = dict()
|
||||
|
||||
for wire in range(num_wires):
|
||||
num_uphill = 0
|
||||
num_downhill = 0
|
||||
num_bidir = 0
|
||||
num_bels_downhill = 0
|
||||
|
||||
if wire in wire_uphill:
|
||||
num_uphill = len(wire_uphill[wire])
|
||||
print("static WireDelayPOD wire%d_uphill[] = {" % wire)
|
||||
print(",\n".join([" {%d, 1.0}" % other_wire for other_wire in wire_uphill[wire]]))
|
||||
print("};")
|
||||
pips = list()
|
||||
for src in wire_uphill[wire]:
|
||||
if (src, wire) not in pipcache:
|
||||
pipcache[(src, wire)] = len(pipinfo)
|
||||
pipinfo.append(" {%d, %d, 1.0}" % (src, wire))
|
||||
pips.append("%d" % pipcache[(src, wire)])
|
||||
num_uphill = len(pips)
|
||||
list_uphill = "wire%d_uppips" % wire
|
||||
print("static int wire%d_uppips[] = {%s};" % (wire, ", ".join(pips)))
|
||||
else:
|
||||
num_uphill = 0
|
||||
list_uphill = "nullptr"
|
||||
|
||||
if wire in wire_downhill:
|
||||
num_downhill = len(wire_downhill[wire])
|
||||
print("static WireDelayPOD wire%d_downhill[] = {" % wire)
|
||||
print(",\n".join([" {%d, 1.0}" % other_wire for other_wire in wire_downhill[wire]]))
|
||||
print("};")
|
||||
|
||||
if wire in wire_bidir:
|
||||
num_bidir = len(wire_bidir[wire])
|
||||
print("static WireDelayPOD wire%d_bidir[] = {" % wire)
|
||||
print(",\n".join([" {%d, 1.0}" % other_wire for other_wire in wire_bidir[wire]]))
|
||||
print("};")
|
||||
pips = list()
|
||||
for dst in wire_downhill[wire]:
|
||||
if (wire, dst) not in pipcache:
|
||||
pipcache[(wire, dst)] = len(pipinfo)
|
||||
pipinfo.append(" {%d, %d, 1.0}" % (wire, dst))
|
||||
pips.append("%d" % pipcache[(wire, dst)])
|
||||
num_downhill = len(pips)
|
||||
list_downhill = "wire%d_downpips" % wire
|
||||
print("static int wire%d_downpips[] = {%s};" % (wire, ", ".join(pips)))
|
||||
else:
|
||||
num_downhill = 0
|
||||
list_downhill = "nullptr"
|
||||
|
||||
if wire in wire_downhill_belports:
|
||||
num_bels_downhill = len(wire_downhill_belports[wire])
|
||||
print("static BelPortPOD wire%d_downbels[] = {" % wire)
|
||||
print(",\n".join([" {%d, PIN_%s}" % it for it in wire_downhill_belports[wire]]))
|
||||
print("};")
|
||||
else:
|
||||
num_bels_downhill = 0
|
||||
|
||||
info = " {"
|
||||
info += "\"%d_%d_%s\", " % wire_names_r[wire]
|
||||
info += "%d, %d, %d, " % (num_uphill, num_downhill, num_bidir)
|
||||
info += ("wire%d_uphill, " % wire) if num_uphill > 0 else "nullptr, "
|
||||
info += ("wire%d_downhill, " % wire) if num_downhill > 0 else "nullptr, "
|
||||
info += ("wire%d_bidir, " % wire) if num_bidir > 0 else "nullptr, "
|
||||
info += "%d, " % (num_bels_downhill)
|
||||
info += "%d, %d, %s, %s, %d, " % (num_uphill, num_downhill, list_uphill, list_downhill, num_bels_downhill)
|
||||
|
||||
if wire in wire_uphill_belport:
|
||||
info += "{%d, PIN_%s}, " % wire_uphill_belport[wire]
|
||||
@ -278,7 +289,15 @@ for wire in range(num_wires):
|
||||
|
||||
wireinfo.append(info)
|
||||
|
||||
print("int num_wires_%s = %d;" % (dev_name, num_wires))
|
||||
print("WireInfoPOD wire_data_%s[%d] = {" % (dev_name, num_wires))
|
||||
print("static WireInfoPOD wire_data_%s[%d] = {" % (dev_name, num_wires))
|
||||
print(",\n".join(wireinfo))
|
||||
print("};")
|
||||
|
||||
print("static PipInfoPOD pip_data_%s[%d] = {" % (dev_name, len(pipinfo)))
|
||||
print(",\n".join(pipinfo))
|
||||
print("};")
|
||||
|
||||
print("ChipInfoPOD chip_info_%s = {" % dev_name)
|
||||
print(" %d, %d, %d," % (len(bel_name), num_wires, len(pipinfo)))
|
||||
print(" bel_data_%s, wire_data_%s, pip_data_%s" % (dev_name, dev_name, dev_name))
|
||||
print("};")
|
||||
|
||||
@ -52,6 +52,9 @@ void arch_wrap_python() {
|
||||
.def("getBels", &Chip::getBels)
|
||||
.def("getWires", &Chip::getWires);
|
||||
|
||||
WRAP_RANGE(AllWire);
|
||||
|
||||
WRAP_RANGE(Bel);
|
||||
WRAP_RANGE(BelPin);
|
||||
WRAP_RANGE(Wire);
|
||||
WRAP_RANGE(AllPip);
|
||||
WRAP_RANGE(Pip);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user