add missing bind and lutperm
This commit is contained in:
Miodrag Milanovic
myrtle
parent
7f8518d938
commit
62ace58204
@ -127,6 +127,29 @@ Arch::Arch(ArchArgs args) : args(args)
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y_ids.push_back(y_id);
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id_to_y[y_id] = i;
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}
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wire_tile_vecidx.resize(chip_info->num_tiles, -1);
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int n_wires = 0;
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for (auto e : getWires()) {
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if (e.index == 0) {
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wire_tile_vecidx.at(e.location.y * chip_info->width + e.location.x) = n_wires;
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}
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n_wires++;
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}
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wire2net.resize(n_wires, nullptr);
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wire_fanout.resize(n_wires, 0);
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pip_tile_vecidx.resize(chip_info->num_tiles, -1);
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int n_pips = 0;
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for (auto e : getPips()) {
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if (e.index == 0) {
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pip_tile_vecidx.at(e.location.y * chip_info->width + e.location.x) = n_pips;
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}
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n_pips++;
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}
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pip2net.resize(n_pips, nullptr);
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lutperm_allowed.resize(chip_info->width * chip_info->height * 4);
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}
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void Arch::list_devices()
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@ -395,6 +418,9 @@ bool Arch::place()
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bool Arch::route()
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{
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std::string router = str_or_default(settings, id_router, defaultRouter);
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disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
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bool result;
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if (router == "router1") {
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result = router1(getCtx(), Router1Cfg(getCtx()));
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@ -503,4 +529,16 @@ std::vector<std::pair<std::string, std::string>> Arch::get_tiles_at_loc(int row,
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return ret;
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}
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// -----------------------------------------------------------------------
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std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const
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{
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std::vector<std::pair<IdString, std::string>> ret;
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auto &wi = tile_info(wire)->wire_data[wire.index];
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ret.push_back(std::make_pair(id_TILE_WIRE_ID, stringf("%d", wi.tile_wire)));
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return ret;
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}
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NEXTPNR_NAMESPACE_END
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233
machxo2/arch.h
233
machxo2/arch.h
@ -66,6 +66,11 @@ NPNR_PACKED_STRUCT(struct PipInfoPOD {
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int16_t padding2;
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});
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inline bool is_lutperm_pip(int16_t flags) { return flags & 0x4000; }
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inline uint8_t lutperm_lut(int16_t flags) { return (flags >> 4) & 0x7; }
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inline uint8_t lutperm_out(int16_t flags) { return (flags >> 2) & 0x3; }
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inline uint8_t lutperm_in(int16_t flags) { return flags & 0x3; }
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NPNR_PACKED_STRUCT(struct PipLocatorPOD {
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LocationPOD rel_loc;
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int32_t index;
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@ -383,6 +388,15 @@ struct Arch : BaseArch<ArchRanges>
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// inverse of the above for name->object mapping
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dict<IdString, int> id_to_x, id_to_y;
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enum class LutPermRule
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{
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NONE,
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CARRY,
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ALL,
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};
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std::vector<LutPermRule> lutperm_allowed;
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bool disable_router_lutperm = false;
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enum LogicBELType
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{
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BEL_COMB = 0,
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@ -415,6 +429,17 @@ struct Arch : BaseArch<ArchRanges>
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mutable std::vector<TileStatus> tile_status;
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// faster replacements for base_pip2net, base_wire2net
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// indexed by get_pip_vecidx()
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std::vector<NetInfo *> pip2net;
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// indexed by get_wire_vecidx()
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std::vector<NetInfo *> wire2net;
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std::vector<int> wire_fanout;
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// We record the index=0 offset into pip2net for each tile, allowing us to
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// calculate any PipId's offset from pip.index and pip.location
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std::vector<int32_t> pip_tile_vecidx;
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std::vector<int32_t> wire_tile_vecidx;
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// Helpers
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template <typename Id> const TileTypePOD *tile_info(Id &id) const
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{
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@ -470,6 +495,62 @@ struct Arch : BaseArch<ArchRanges>
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return IdStringList(ids);
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}
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uint32_t getBelChecksum(BelId bel) const override { return bel.index; }
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int get_slice_index(int x, int y, int slice) const
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{
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NPNR_ASSERT(slice >= 0 && slice < 4);
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return (y * chip_info->width + x) * 4 + slice;
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}
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void update_bel(BelId bel, CellInfo *old_cell, CellInfo *new_cell)
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{
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CellInfo *act_cell = (old_cell == nullptr) ? new_cell : old_cell;
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if (act_cell->type.in(id_TRELLIS_FF, id_TRELLIS_COMB, id_TRELLIS_RAMW)) {
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LogicTileStatus *lts = tile_status.at(tile_index(bel)).lts;
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NPNR_ASSERT(lts != nullptr);
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int z = tile_info(bel)->bel_data[bel.index].z;
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lts->slices[(z >> lc_idx_shift) / 2].dirty = true;
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if (act_cell->type == id_TRELLIS_FF)
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lts->tile_dirty = true; // because FF CLK/LSR signals are tile-wide
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if (act_cell->type == id_TRELLIS_COMB && (act_cell->combInfo.flags & ArchCellInfo::COMB_LUTRAM))
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lts->tile_dirty = true; // because RAM shares CLK/LSR signals with FFs
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lts->cells[z] = new_cell;
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}
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}
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
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{
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NPNR_ASSERT(bel != BelId());
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auto &slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
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NPNR_ASSERT(slot == nullptr);
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slot = cell;
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cell->bel = bel;
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cell->belStrength = strength;
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if (getBelType(bel) == id_TRELLIS_COMB) {
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int flags = cell->combInfo.flags;
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lutperm_allowed.at(
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get_slice_index(bel.location.x, bel.location.y, (getBelLocation(bel).z >> lc_idx_shift) / 2)) =
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(((flags & ArchCellInfo::COMB_LUTRAM) || (flags & ArchCellInfo::COMB_RAMW_BLOCK))
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? LutPermRule::NONE
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: ((flags & ArchCellInfo::COMB_CARRY) ? LutPermRule::CARRY : LutPermRule::ALL));
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}
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update_bel(bel, nullptr, cell);
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refreshUiBel(bel);
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}
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void unbindBel(BelId bel) override
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{
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NPNR_ASSERT(bel != BelId());
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auto &slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
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NPNR_ASSERT(slot != nullptr);
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update_bel(bel, slot, nullptr);
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slot->bel = BelId();
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slot->belStrength = STRENGTH_NONE;
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slot = nullptr;
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refreshUiBel(bel);
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}
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Loc getBelLocation(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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@ -484,6 +565,27 @@ struct Arch : BaseArch<ArchRanges>
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BelRange getBelsByTile(int x, int y) const override;
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bool getBelGlobalBuf(BelId bel) const override;
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bool checkBelAvail(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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const CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
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return slot == nullptr;
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}
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CellInfo *getBoundBelCell(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
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return slot;
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}
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CellInfo *getConflictingBelCell(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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CellInfo *slot = tile_status.at(tile_index(bel)).boundcells.at(bel.index);
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return slot;
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}
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BelRange getBels() const override
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{
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BelRange range;
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@ -523,6 +625,60 @@ struct Arch : BaseArch<ArchRanges>
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return IdStringList(ids);
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}
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IdString getWireType(WireId wire) const override
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{
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NPNR_ASSERT(wire != WireId());
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IdString id;
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id.index = tile_info(wire)->wire_data[wire.index].type;
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return id;
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}
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std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId) const override;
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uint32_t getWireChecksum(WireId wire) const override { return wire.index; }
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uint32_t get_wire_vecidx(const WireId &e) const
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{
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uint32_t tile = e.location.y * chip_info->width + e.location.x;
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int32_t base = wire_tile_vecidx.at(tile);
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NPNR_ASSERT(base != -1);
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int32_t i = base + e.index;
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return i;
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}
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override
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{
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NPNR_ASSERT(wire != WireId());
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auto &w2n_entry = wire2net.at(get_wire_vecidx(wire));
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NPNR_ASSERT(w2n_entry == nullptr);
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net->wires[wire].pip = PipId();
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net->wires[wire].strength = strength;
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w2n_entry = net;
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this->refreshUiWire(wire);
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}
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void unbindWire(WireId wire) override
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{
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NPNR_ASSERT(wire != WireId());
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auto &w2n_entry = wire2net.at(get_wire_vecidx(wire));
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NPNR_ASSERT(w2n_entry != nullptr);
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auto &net_wires = w2n_entry->wires;
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auto it = net_wires.find(wire);
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NPNR_ASSERT(it != net_wires.end());
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auto pip = it->second.pip;
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if (pip != PipId()) {
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pip2net.at(get_pip_vecidx(pip)) = nullptr;
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wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]--;
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}
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net_wires.erase(it);
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w2n_entry = nullptr;
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this->refreshUiWire(wire);
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}
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virtual bool checkWireAvail(WireId wire) const override { return getBoundWireNet(wire) == nullptr; }
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NetInfo *getBoundWireNet(WireId wire) const override { return wire2net.at(get_wire_vecidx(wire)); }
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DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0.01); }
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WireRange getWires() const override
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@ -568,6 +724,78 @@ struct Arch : BaseArch<ArchRanges>
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PipId getPipByName(IdStringList name) const override;
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IdStringList getPipName(PipId pip) const override;
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uint32_t getPipChecksum(PipId pip) const override { return pip.index; }
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uint32_t get_pip_vecidx(const PipId &e) const
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{
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uint32_t tile = e.location.y * chip_info->width + e.location.x;
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int32_t base = pip_tile_vecidx.at(tile);
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NPNR_ASSERT(base != -1);
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int32_t i = base + e.index;
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return i;
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}
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override
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{
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NPNR_ASSERT(pip != PipId());
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wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]++;
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auto &p2n_entry = pip2net.at(get_pip_vecidx(pip));
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NPNR_ASSERT(p2n_entry == nullptr);
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p2n_entry = net;
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WireId dst = this->getPipDstWire(pip);
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auto &w2n_entry = wire2net.at(get_wire_vecidx(dst));
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NPNR_ASSERT(w2n_entry == nullptr);
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w2n_entry = net;
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net->wires[dst].pip = pip;
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net->wires[dst].strength = strength;
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}
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void unbindPip(PipId pip) override
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{
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NPNR_ASSERT(pip != PipId());
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wire_fanout[get_wire_vecidx(getPipSrcWire(pip))]--;
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auto &p2n_entry = pip2net.at(get_pip_vecidx(pip));
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NPNR_ASSERT(p2n_entry != nullptr);
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WireId dst = this->getPipDstWire(pip);
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auto &w2n_entry = wire2net.at(get_wire_vecidx(dst));
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NPNR_ASSERT(w2n_entry != nullptr);
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w2n_entry = nullptr;
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p2n_entry->wires.erase(dst);
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p2n_entry = nullptr;
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}
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bool is_pip_blocked(PipId pip) const
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{
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auto &pip_data = tile_info(pip)->pip_data[pip.index];
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int lp = pip_data.lutperm_flags;
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if (is_lutperm_pip(lp)) {
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if (disable_router_lutperm)
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return true;
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auto rule = lutperm_allowed.at(get_slice_index(pip.location.x, pip.location.y, lutperm_lut(lp) / 2));
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if (rule == LutPermRule::NONE) {
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// Permutation not allowed
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return true;
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} else if (rule == LutPermRule::CARRY) {
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// Can swap A/B and C/D only
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int i = lutperm_out(lp), j = lutperm_in(lp);
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if ((i / 2) != (j / 2))
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return true;
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}
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}
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return false;
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}
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bool checkPipAvail(PipId pip) const override { return (getBoundPipNet(pip) == nullptr) && !is_pip_blocked(pip); }
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bool checkPipAvailForNet(PipId pip, const NetInfo *net) const override
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{
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NetInfo *bound_net = getBoundPipNet(pip);
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return (bound_net == nullptr || bound_net == net) && !is_pip_blocked(pip);
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}
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NetInfo *getBoundPipNet(PipId pip) const override { return pip2net.at(get_pip_vecidx(pip)); }
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AllPipRange getPips() const override
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{
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AllPipRange range;
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@ -648,6 +876,11 @@ struct Arch : BaseArch<ArchRanges>
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NPNR_ASSERT_FALSE("failed to find Pip tile");
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}
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std::string get_pip_tiletype(PipId pip) const
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{
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return chip_info->tiletype_names[tile_info(pip)->pip_data[pip.index].tile_type].get();
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}
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// Delay
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delay_t estimateDelay(WireId src, WireId dst) const override;
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delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const override;
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@ -404,6 +404,55 @@ static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
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}
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}
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static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init)
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{
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std::array<std::vector<unsigned>, 4> phys_to_log;
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const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D};
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for (unsigned i = 0; i < 4; i++) {
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WireId pin_wire = ctx->getBelPinWire(cell->bel, ports[i]);
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for (PipId pip : ctx->getPipsUphill(pin_wire)) {
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if (!ctx->getBoundPipNet(pip))
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continue;
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unsigned lp = ctx->tile_info(pip)->pip_data[pip.index].lutperm_flags;
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if (!is_lutperm_pip(lp)) { // non-permuting
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phys_to_log[i].push_back(i);
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} else { // permuting
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unsigned from_pin = lutperm_in(lp);
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unsigned to_pin = lutperm_out(lp);
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NPNR_ASSERT(to_pin == i);
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phys_to_log[from_pin].push_back(i);
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}
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}
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}
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for (unsigned i = 0; i < 4; i++)
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if (!phys_to_log.at(i).empty())
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used_phys_pins.insert(ports.at(i));
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if (cell->combInfo.flags & ArchCellInfo::COMB_CARRY) {
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// Insert dummy entries to ensure we keep the split between the two halves of a CCU2
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for (unsigned i = 0; i < 4; i++) {
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if (!phys_to_log.at(i).empty())
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continue;
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for (unsigned j = 2 * (i / 2); j < 2 * ((i / 2) + 1); j++) {
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if (!ctx->getBoundWireNet(ctx->getBelPinWire(cell->bel, ports[j])))
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phys_to_log.at(i).push_back(j);
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}
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}
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}
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unsigned permuted_init = 0;
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for (unsigned i = 0; i < 16; i++) {
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unsigned log_idx = 0;
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for (unsigned j = 0; j < 4; j++) {
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if ((i >> j) & 0x1) {
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for (auto log_pin : phys_to_log[j])
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log_idx |= (1 << log_pin);
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}
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}
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if ((orig_init >> log_idx) & 0x1)
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permuted_init |= (1 << i);
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}
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return permuted_init;
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}
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static std::vector<bool> int_to_bitvector(int val, int size)
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{
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std::vector<bool> bv;
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@ -526,7 +575,8 @@ void write_bitstream(Context *ctx, std::string text_config_file)
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return;
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int lut_init = int_or_default(ci->params, id_INITVAL);
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cc.tiles[tname].add_enum(slice + ".MODE", mode);
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cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT", int_to_bitvector(lut_init, 16));
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cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
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int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, lut_init), 16));
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if (mode == "CCU2") {
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cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
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} else {
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@ -126,6 +126,7 @@ X(NOM_FREQ)
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X(VCC)
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X(WIRE_TYPE_NONE)
|
||||
X(TILE_WIRE_ID)
|
||||
|
||||
X(machxo2)
|
||||
X(pack)
|
||||
|
||||
@ -51,6 +51,7 @@ po::options_description MachXO2CommandHandler::getArchOptions()
|
||||
specific.add_options()("list-devices", "list all supported device names");
|
||||
specific.add_options()("textcfg", po::value<std::string>(), "textual configuration in Trellis format to write");
|
||||
// specific.add_options()("lpf", po::value<std::vector<std::string>>(), "LPF pin constraint file(s)");
|
||||
specific.add_options()("disable-router-lutperm", "don't allow the router to permute LUT inputs");
|
||||
|
||||
return specific;
|
||||
}
|
||||
@ -76,6 +77,8 @@ std::unique_ptr<Context> MachXO2CommandHandler::createContext(dict<std::string,
|
||||
}
|
||||
chipArgs.device = vm["device"].as<std::string>();
|
||||
auto ctx = std::unique_ptr<Context>(new Context(chipArgs));
|
||||
if (vm.count("disable-router-lutperm"))
|
||||
ctx->settings[ctx->id("arch.disable_router_lutperm")] = 1;
|
||||
return ctx;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user