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Rename getWireBelPin to getBelPinWire

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-07-22 10:59:21 +02:00
parent c6e4ad3227
commit 62b66e0208
12 changed files with 26 additions and 26 deletions
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4
common/nextpnr.cc
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@ -67,7 +67,7 @@ WireId Context::getNetinfoSourceWire(NetInfo *net_info) const
if (driver_port_it != net_info->driver.cell->pins.end())
driver_port = driver_port_it->second;
return getWireBelPin(src_bel, portPinFromId(driver_port));
return getBelPinWire(src_bel, portPinFromId(driver_port));
}
WireId Context::getNetinfoSinkWire(NetInfo *net_info, int user_idx) const
@ -85,7 +85,7 @@ WireId Context::getNetinfoSinkWire(NetInfo *net_info, int user_idx) const
if (user_port_it != user_info.cell->pins.end())
user_port = user_port_it->second;
return getWireBelPin(dst_bel, portPinFromId(user_port));
return getBelPinWire(dst_bel, portPinFromId(user_port));
}
delay_t Context::getNetinfoRouteDelay(NetInfo *net_info, int user_idx) const

4
common/place_common.cc
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@ -36,7 +36,7 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
if (driver_cell->bel == BelId())
return 0;
ctx->estimatePosition(driver_cell->bel, driver_x, driver_y, driver_gb);
WireId drv_wire = ctx->getWireBelPin(driver_cell->bel, ctx->portPinFromId(net->driver.port));
WireId drv_wire = ctx->getBelPinWire(driver_cell->bel, ctx->portPinFromId(net->driver.port));
if (driver_gb)
return 0;
float worst_slack = 1000;
@ -48,7 +48,7 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
if (load_cell->bel == BelId())
continue;
if (ctx->timing_driven && type == MetricType::COST) {
WireId user_wire = ctx->getWireBelPin(load_cell->bel, ctx->portPinFromId(load.port));
WireId user_wire = ctx->getBelPinWire(load_cell->bel, ctx->portPinFromId(load.port));
delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
float slack = ctx->getDelayNS(load.budget) - ctx->getDelayNS(raw_wl);
if (slack < 0)

2
ecp5/arch.cc
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@ -206,7 +206,7 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
return br;
}
WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
{
WireId ret;

2
ecp5/arch.h
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@ -484,7 +484,7 @@ struct Arch : BaseCtx
return locInfo(bel)->bel_data[bel.index].type;
}
WireId getWireBelPin(BelId bel, PortPin pin) const;
WireId getBelPinWire(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const
{

2
generic/arch.cc
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@ -215,7 +215,7 @@ const std::vector<BelId> &Arch::getBelsByType(BelType type) const
BelType Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
WireId Arch::getWireBelPin(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).wire; }
WireId Arch::getBelPinWire(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).wire; }
BelPin Arch::getBelPinUphill(WireId wire) const { return wires.at(wire).uphill_bel_pin; }

2
generic/arch.h
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@ -145,7 +145,7 @@ struct Arch : BaseCtx
const std::vector<BelId> &getBels() const;
const std::vector<BelId> &getBelsByType(BelType type) const;
BelType getBelType(BelId bel) const;
WireId getWireBelPin(BelId bel, PortPin pin) const;
WireId getBelPinWire(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const;
const std::vector<BelPin> &getBelPinsDownhill(WireId wire) const;

2
ice40/arch.cc
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@ -308,7 +308,7 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
return br;
}
WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
{
WireId ret;

2
ice40/arch.h
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@ -465,7 +465,7 @@ struct Arch : BaseCtx
return chip_info->bel_data[bel.index].type;
}
WireId getWireBelPin(BelId bel, PortPin pin) const;
WireId getBelPinWire(BelId bel, PortPin pin) const;
BelPin getBelPinUphill(WireId wire) const
{

2
ice40/arch_place.cc
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@ -110,7 +110,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
} else if (cell->type == id_sb_gb) {
NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr);
const NetInfo *net = cell->ports.at(id_glb_buf_out).net;
IdString glb_net = getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT));
IdString glb_net = getWireName(getBelPinWire(bel, PIN_GLOBAL_BUFFER_OUTPUT));
int glb_id = std::stoi(std::string("") + glb_net.str(this).back());
if (net->is_reset && net->is_enable)
return false;

4
ice40/arch_pybindings.cc
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@ -82,8 +82,8 @@ void arch_wrap_python()
fn_wrapper_1a<Context, decltype(&Context::getBelsAtSameTile), &Context::getBelsAtSameTile, wrap_context<BelRange>,
conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelsAtSameTile");
fn_wrapper_2a<Context, decltype(&Context::getWireBelPin), &Context::getWireBelPin, conv_to_str<WireId>,
conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getWireBelPin");
fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire");
fn_wrapper_1a<Context, decltype(&Context::getBelPinUphill), &Context::getBelPinUphill, wrap_context<BelPin>,
conv_from_str<WireId>>::def_wrap(ctx_cls, "getBelPinUphill");
fn_wrapper_1a<Context, decltype(&Context::getBelPinsDownhill), &Context::getBelPinsDownhill,

6
ice40/bitstream.cc
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@ -319,8 +319,8 @@ void write_asc(const Context *ctx, std::ostream &out)
NPNR_ASSERT(iez != -1);
bool input_en = false;
if ((ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) ||
(ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) {
if ((ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_0).index] != IdString()) ||
(ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_1).index] != IdString())) {
input_en = true;
}
@ -762,7 +762,7 @@ bool read_asc(Context *ctx, std::istream &in)
if (cell.second->bel != BelId()) {
for (auto &port : cell.second->ports) {
PortPin pin = ctx->portPinFromId(port.first);
WireId wire = ctx->getWireBelPin(cell.second->bel, pin);
WireId wire = ctx->getBelPinWire(cell.second->bel, pin);
if (wire != WireId()) {
IdString name = ctx->getBoundWireNet(wire);
if (name != IdString()) {

20
ice40/main.cc
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@ -322,25 +322,25 @@ int main(int argc, char *argv[])
src_wires.push_back(w);*/
for (auto b : ctx->getBels()) {
if (ctx->getBelType(b) == TYPE_ICESTORM_LC) {
src_wires.push_back(ctx->getWireBelPin(b, PIN_O));
src_wires.push_back(ctx->getBelPinWire(b, PIN_O));
}
if (ctx->getBelType(b) == TYPE_SB_IO) {
src_wires.push_back(ctx->getWireBelPin(b, PIN_D_IN_0));
src_wires.push_back(ctx->getBelPinWire(b, PIN_D_IN_0));
}
}
for (auto b : ctx->getBels()) {
if (ctx->getBelType(b) == TYPE_ICESTORM_LC) {
dst_wires.push_back(ctx->getWireBelPin(b, PIN_I0));
dst_wires.push_back(ctx->getWireBelPin(b, PIN_I1));
dst_wires.push_back(ctx->getWireBelPin(b, PIN_I2));
dst_wires.push_back(ctx->getWireBelPin(b, PIN_I3));
dst_wires.push_back(ctx->getWireBelPin(b, PIN_CEN));
dst_wires.push_back(ctx->getWireBelPin(b, PIN_CIN));
dst_wires.push_back(ctx->getBelPinWire(b, PIN_I0));
dst_wires.push_back(ctx->getBelPinWire(b, PIN_I1));
dst_wires.push_back(ctx->getBelPinWire(b, PIN_I2));
dst_wires.push_back(ctx->getBelPinWire(b, PIN_I3));
dst_wires.push_back(ctx->getBelPinWire(b, PIN_CEN));
dst_wires.push_back(ctx->getBelPinWire(b, PIN_CIN));
}
if (ctx->getBelType(b) == TYPE_SB_IO) {
dst_wires.push_back(ctx->getWireBelPin(b, PIN_D_OUT_0));
dst_wires.push_back(ctx->getWireBelPin(b, PIN_OUTPUT_ENABLE));
dst_wires.push_back(ctx->getBelPinWire(b, PIN_D_OUT_0));
dst_wires.push_back(ctx->getBelPinWire(b, PIN_OUTPUT_ENABLE));
}
}