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interchange: Don't error out on missing cell ports

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This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-04-25 16:29:13 +01:00
parent a146dbdb03
commit 64f5b1d031
2 changed files with 3 additions and 2 deletions
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2
fpga_interchange/site_arch.cc
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@ -136,6 +136,8 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site
bool have_vcc_pins = false;
for (CellInfo *cell : site_info->cells_in_site) {
for (const auto &pin_pair : cell->cell_bel_pins) {
if (!cell->ports.count(pin_pair.first))
continue;
const PortInfo &port = cell->ports.at(pin_pair.first);
if (port.net != nullptr) {
nets.emplace(port.net, SiteNetInfo{port.net});

3
fpga_interchange/site_router.cc
View File

@ -59,8 +59,7 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info)
BelId bel = cell->bel;
for (const auto &pin_pair : cell->cell_bel_pins) {
if (!cell->ports.count(pin_pair.first))
log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx),
pin_pair.first.c_str(ctx));
continue;
const PortInfo &port = cell->ports.at(pin_pair.first);
NPNR_ASSERT(port.net != nullptr);