gowin: Himbaechel. Handling of disabled units
Using extra cell functions to mark disabled units using the PLL example. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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@ -190,6 +190,10 @@ struct GowinGlobalRouter
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NPNR_ASSERT(driver.cell->bel != BelId());
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NPNR_ASSERT(driver.cell->bel != BelId());
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IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
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IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
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for (size_t i = 0; i < pin_func.size(); ++i) {
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for (size_t i = 0; i < pin_func.size(); ++i) {
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if (ctx->debug) {
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log_info("bel:%s, pin func: %lu:%s\n", ctx->nameOfBel(driver.cell->bel), i,
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pin_func[i].str(ctx).c_str());
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}
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if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
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if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
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if (ctx->debug) {
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if (ctx->debug) {
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log_info("Clock pin:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
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log_info("Clock pin:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),
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@ -113,14 +113,10 @@ void GowinImpl::init(Context *ctx)
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}
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}
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}
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}
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if (ctx->debug) {
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// log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
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log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
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}
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for (int i = 0; i < ctx->chip_info->packages.ssize(); ++i) {
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for (int i = 0; i < ctx->chip_info->packages.ssize(); ++i) {
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if (IdString(ctx->chip_info->packages[i].name) == package_idx) {
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if (IdString(ctx->chip_info->packages[i].name) == package_idx) {
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if (ctx->debug) {
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// log_info("i:%d %s\n", i, package_idx.c_str(ctx));
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log_info("i:%d %s\n", i, package_idx.c_str(ctx));
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}
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ctx->package_info = &ctx->chip_info->packages[i];
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ctx->package_info = &ctx->chip_info->packages[i];
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break;
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break;
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}
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}
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@ -565,9 +565,18 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
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tiletype = f"{typename}_{ttyp}"
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tiletype = f"{typename}_{ttyp}"
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if tdesc.sfx != 0:
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if tdesc.sfx != 0:
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tiletype += f"_{tdesc.sfx}"
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tiletype += f"_{tdesc.sfx}"
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# disabled PLLs
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if tdesc.extra_func and 'disabled' in tdesc.extra_func and 'PLL' in tdesc.extra_func['disabled']:
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tiletype += '_disabled'
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tt = chip.create_tile_type(tiletype)
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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tdesc.tiletype = tiletype
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return tt
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tt = chip.create_tile_type(tiletype)
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tt = chip.create_tile_type(tiletype)
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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tt.extra_data = TileExtraData(chip.strs.id(typename))
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# wires
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# wires
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if chip.name == 'GW1NS-4':
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if chip.name == 'GW1NS-4':
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pll_name = 'PLLVR'
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pll_name = 'PLLVR'
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