gowin: Switch to BaseArch
Signed-off-by: D. Shah <dave@ds0.me>
This commit is contained in:
D. Shah
parent
c7ef7e1902
commit
6575bfac3e
@ -736,17 +736,8 @@ Arch::Arch(ArchArgs args) : args(args)
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}
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}
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}
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// Dummy for empty decals
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decal_graphics[IdString()];
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std::unordered_set<IdString> bel_types;
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for (BelId bel : getBels()) {
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bel_types.insert(getBelType(bel));
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}
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for (IdString bel_type : bel_types) {
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cell_types.push_back(bel_type);
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}
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BaseArch::init_cell_types();
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BaseArch::init_bel_buckets();
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}
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void IdString::initialize_arch(const BaseCtx *ctx)
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@ -785,8 +776,6 @@ const std::vector<BelId> &Arch::getBelsByTile(int x, int y) const { return bels_
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bool Arch::getBelGlobalBuf(BelId bel) const { return bels.at(bel).gb; }
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uint32_t Arch::getBelChecksum(BelId bel) const { return bel.index; }
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void Arch::bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
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{
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bels.at(bel).bound_cell = cell;
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@ -848,12 +837,6 @@ IdString Arch::getWireType(WireId wire) const { return wires.at(wire).type; }
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const std::map<IdString, std::string> &Arch::getWireAttrs(WireId wire) const { return wires.at(wire).attrs; }
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uint32_t Arch::getWireChecksum(WireId wire) const
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{
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// FIXME
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return 0;
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}
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void Arch::bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
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{
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wires.at(wire).bound_net = net;
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@ -902,8 +885,6 @@ IdString Arch::getPipType(PipId pip) const { return pips.at(pip).type; }
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const std::map<IdString, std::string> &Arch::getPipAttrs(PipId pip) const { return pips.at(pip).attrs; }
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uint32_t Arch::getPipChecksum(PipId wire) const { return wire.index; }
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void Arch::bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
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{
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WireId wire = pips.at(pip).dstWire;
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@ -1074,25 +1055,6 @@ bool Arch::route()
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// ---------------------------------------------------------------
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const std::vector<GraphicElement> &Arch::getDecalGraphics(DecalId decal) const
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{
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if (!decal_graphics.count(decal)) {
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std::cerr << "No decal named " << decal.str(this) << std::endl;
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log_error("No decal named %s!\n", decal.c_str(this));
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}
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return decal_graphics.at(decal);
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}
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DecalXY Arch::getBelDecal(BelId bel) const { return bels.at(bel).decalxy; }
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DecalXY Arch::getWireDecal(WireId wire) const { return wires.at(wire).decalxy; }
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DecalXY Arch::getPipDecal(PipId pip) const { return pips.at(pip).decalxy; }
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DecalXY Arch::getGroupDecal(GroupId group) const { return groups.at(group).decalxy; }
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// ---------------------------------------------------------------
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bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
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{
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if (!cellTiming.count(cell->name))
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205
gowin/arch.h
205
gowin/arch.h
@ -243,7 +243,37 @@ struct CellTiming
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std::unordered_map<IdString, std::vector<TimingClockingInfo>> clockingInfo;
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};
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struct Arch : BaseCtx
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struct ArchRanges
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{
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// Bels
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using AllBelsRange = const std::vector<BelId> &;
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using TileBelsRange = const std::vector<BelId> &;
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using BelAttrsRange = const std::map<IdString, std::string> &;
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using BelPinsRange = std::vector<IdString>;
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// Wires
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using AllWiresRange = const std::vector<WireId> &;
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using DownhillPipRange = const std::vector<PipId> &;
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using UphillPipRange = const std::vector<PipId> &;
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using WireBelPinRange = const std::vector<BelPin> &;
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using WireAttrsRange = const std::map<IdString, std::string> &;
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// Pips
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using AllPipsRange = const std::vector<PipId> &;
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using PipAttrsRange = const std::map<IdString, std::string> &;
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// Groups
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using AllGroupsRange = std::vector<GroupId>;
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using GroupBelsRange = const std::vector<BelId> &;
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using GroupWiresRange = const std::vector<WireId> &;
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using GroupPipsRange = const std::vector<PipId> &;
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using GroupGroupsRange = const std::vector<GroupId> &;
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// Decals
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using DecalGfxRange = const std::vector<GraphicElement> &;
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// Placement validity
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using CellTypeRange = std::vector<IdString>;
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using BelBucketRange = std::vector<BelBucketId>;
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using BucketBelRange = std::vector<BelId>;
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};
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struct Arch : BaseArch<ArchRanges>
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{
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std::string family;
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std::string device;
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@ -313,14 +343,13 @@ struct Arch : BaseCtx
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ArchArgs args;
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Arch(ArchArgs args);
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std::string getChipName() const { return device; }
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std::string getChipName() const override { return device; }
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IdString archId() const { return id("gowin"); }
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ArchArgs archArgs() const { return args; }
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IdString archArgsToId(ArchArgs args) const { return id("none"); }
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int getGridDimX() const { return gridDimX; }
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int getGridDimY() const { return gridDimY; }
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int getGridDimX() const override { return gridDimX; }
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int getGridDimY() const override { return gridDimY; }
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int getTileBelDimZ(int x, int y) const { return tileBelDimZ[x][y]; }
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int getTilePipDimZ(int x, int y) const { return tilePipDimZ[x][y]; }
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char getNameDelimiter() const
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@ -328,74 +357,71 @@ struct Arch : BaseCtx
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return ' '; /* use a non-existent delimiter as we aren't using IdStringLists yet */
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}
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BelId getBelByName(IdStringList name) const;
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IdStringList getBelName(BelId bel) const;
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Loc getBelLocation(BelId bel) const;
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BelId getBelByLocation(Loc loc) const;
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const std::vector<BelId> &getBelsByTile(int x, int y) const;
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bool getBelGlobalBuf(BelId bel) const;
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uint32_t getBelChecksum(BelId bel) const;
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength);
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void unbindBel(BelId bel);
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bool checkBelAvail(BelId bel) const;
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CellInfo *getBoundBelCell(BelId bel) const;
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CellInfo *getConflictingBelCell(BelId bel) const;
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const std::vector<BelId> &getBels() const;
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IdString getBelType(BelId bel) const;
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const std::map<IdString, std::string> &getBelAttrs(BelId bel) const;
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WireId getBelPinWire(BelId bel, IdString pin) const;
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PortType getBelPinType(BelId bel, IdString pin) const;
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std::vector<IdString> getBelPins(BelId bel) const;
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BelId getBelByName(IdStringList name) const override;
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IdStringList getBelName(BelId bel) const override;
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Loc getBelLocation(BelId bel) const override;
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BelId getBelByLocation(Loc loc) const override;
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const std::vector<BelId> &getBelsByTile(int x, int y) const override;
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bool getBelGlobalBuf(BelId bel) const override;
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override;
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void unbindBel(BelId bel) override;
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bool checkBelAvail(BelId bel) const override;
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CellInfo *getBoundBelCell(BelId bel) const override;
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CellInfo *getConflictingBelCell(BelId bel) const override;
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const std::vector<BelId> &getBels() const override;
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IdString getBelType(BelId bel) const override;
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const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override;
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WireId getBelPinWire(BelId bel, IdString pin) const override;
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PortType getBelPinType(BelId bel, IdString pin) const override;
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std::vector<IdString> getBelPins(BelId bel) const override;
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WireId getWireByName(IdStringList name) const;
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IdStringList getWireName(WireId wire) const;
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IdString getWireType(WireId wire) const;
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const std::map<IdString, std::string> &getWireAttrs(WireId wire) const;
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uint32_t getWireChecksum(WireId wire) const;
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength);
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void unbindWire(WireId wire);
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bool checkWireAvail(WireId wire) const;
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NetInfo *getBoundWireNet(WireId wire) const;
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WireId getConflictingWireWire(WireId wire) const { return wire; }
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NetInfo *getConflictingWireNet(WireId wire) const;
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DelayInfo getWireDelay(WireId wire) const { return DelayInfo(); }
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const std::vector<WireId> &getWires() const;
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const std::vector<BelPin> &getWireBelPins(WireId wire) const;
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WireId getWireByName(IdStringList name) const override;
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IdStringList getWireName(WireId wire) const override;
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IdString getWireType(WireId wire) const override;
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const std::map<IdString, std::string> &getWireAttrs(WireId wire) const override;
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override;
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void unbindWire(WireId wire) override;
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bool checkWireAvail(WireId wire) const override;
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NetInfo *getBoundWireNet(WireId wire) const override;
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WireId getConflictingWireWire(WireId wire) const override { return wire; }
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NetInfo *getConflictingWireNet(WireId wire) const override;
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DelayInfo getWireDelay(WireId wire) const override { return DelayInfo(); }
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const std::vector<WireId> &getWires() const override;
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const std::vector<BelPin> &getWireBelPins(WireId wire) const override;
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PipId getPipByName(IdStringList name) const;
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IdStringList getPipName(PipId pip) const;
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IdString getPipType(PipId pip) const;
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const std::map<IdString, std::string> &getPipAttrs(PipId pip) const;
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uint32_t getPipChecksum(PipId pip) const;
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength);
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void unbindPip(PipId pip);
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bool checkPipAvail(PipId pip) const;
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NetInfo *getBoundPipNet(PipId pip) const;
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WireId getConflictingPipWire(PipId pip) const;
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NetInfo *getConflictingPipNet(PipId pip) const;
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const std::vector<PipId> &getPips() const;
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Loc getPipLocation(PipId pip) const;
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WireId getPipSrcWire(PipId pip) const;
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WireId getPipDstWire(PipId pip) const;
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DelayInfo getPipDelay(PipId pip) const;
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const std::vector<PipId> &getPipsDownhill(WireId wire) const;
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const std::vector<PipId> &getPipsUphill(WireId wire) const;
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PipId getPipByName(IdStringList name) const override;
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IdStringList getPipName(PipId pip) const override;
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IdString getPipType(PipId pip) const override;
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const std::map<IdString, std::string> &getPipAttrs(PipId pip) const override;
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override;
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void unbindPip(PipId pip) override;
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bool checkPipAvail(PipId pip) const override;
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NetInfo *getBoundPipNet(PipId pip) const override;
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WireId getConflictingPipWire(PipId pip) const override;
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NetInfo *getConflictingPipNet(PipId pip) const override;
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const std::vector<PipId> &getPips() const override;
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Loc getPipLocation(PipId pip) const override;
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WireId getPipSrcWire(PipId pip) const override;
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WireId getPipDstWire(PipId pip) const override;
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DelayInfo getPipDelay(PipId pip) const override;
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const std::vector<PipId> &getPipsDownhill(WireId wire) const override;
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const std::vector<PipId> &getPipsUphill(WireId wire) const override;
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GroupId getGroupByName(IdStringList name) const;
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IdStringList getGroupName(GroupId group) const;
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std::vector<GroupId> getGroups() const;
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const std::vector<BelId> &getGroupBels(GroupId group) const;
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const std::vector<WireId> &getGroupWires(GroupId group) const;
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const std::vector<PipId> &getGroupPips(GroupId group) const;
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const std::vector<GroupId> &getGroupGroups(GroupId group) const;
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GroupId getGroupByName(IdStringList name) const override;
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IdStringList getGroupName(GroupId group) const override;
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std::vector<GroupId> getGroups() const override;
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const std::vector<BelId> &getGroupBels(GroupId group) const override;
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const std::vector<WireId> &getGroupWires(GroupId group) const override;
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const std::vector<PipId> &getGroupPips(GroupId group) const override;
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const std::vector<GroupId> &getGroupGroups(GroupId group) const override;
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const { return 0.01; }
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delay_t getRipupDelayPenalty() const { return 0.4; }
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float getDelayNS(delay_t v) const { return v; }
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delay_t estimateDelay(WireId src, WireId dst) const override;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
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delay_t getDelayEpsilon() const override { return 0.01; }
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delay_t getRipupDelayPenalty() const override { return 0.4; }
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float getDelayNS(delay_t v) const override { return v; }
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DelayInfo getDelayFromNS(float ns) const
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DelayInfo getDelayFromNS(float ns) const override
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{
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DelayInfo del;
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del.maxRaise = ns;
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@ -405,20 +431,14 @@ struct Arch : BaseCtx
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return del;
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}
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uint32_t getDelayChecksum(delay_t v) const { return 0; }
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bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
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uint32_t getDelayChecksum(delay_t v) const override { return 0; }
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bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
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ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
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ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
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bool pack();
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bool place();
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bool route();
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const std::vector<GraphicElement> &getDecalGraphics(DecalId decal) const;
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DecalXY getBelDecal(BelId bel) const;
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DecalXY getWireDecal(WireId wire) const;
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DecalXY getPipDecal(PipId pip) const;
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DecalXY getGroupDecal(GroupId group) const;
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bool pack() override;
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bool place() override;
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bool route() override;
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bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
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// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
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@ -426,31 +446,6 @@ struct Arch : BaseCtx
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// Get the TimingClockingInfo of a port
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TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
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bool isValidBelForCellType(IdString cell_type, BelId bel) const { return cell_type == getBelType(bel); }
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const std::vector<IdString> &getCellTypes() const { return cell_types; }
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std::vector<BelBucketId> getBelBuckets() const { return cell_types; }
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IdString getBelBucketName(BelBucketId bucket) const { return bucket; }
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BelBucketId getBelBucketByName(IdString name) const { return name; }
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BelBucketId getBelBucketForBel(BelId bel) const { return getBelType(bel); }
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BelBucketId getBelBucketForCellType(IdString cell_type) const { return cell_type; }
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std::vector<BelId> getBelsInBucket(BelBucketId bucket) const
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{
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std::vector<BelId> bels;
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for (BelId bel : getBels()) {
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if (getBelType(bel) == bucket) {
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bels.push_back(bel);
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}
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}
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return bels;
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}
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bool isValidBelForCell(CellInfo *cell, BelId bel) const;
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bool isBelLocationValid(BelId bel) const;
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