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ice40: emit list of upbels in chipdb

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This commit is contained in:
Sergiusz Bazanski 2018-07-24 02:05:30 +01:00
parent fae7994bc3
commit 65ceb20784
4 changed files with 22 additions and 16 deletions
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4
ice40/arch.h
View File

@ -83,8 +83,8 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
int32_t num_uphill, num_downhill;
RelPtr<int32_t> pips_uphill, pips_downhill;
int32_t num_bels_downhill;
BelPortPOD bel_uphill;
int32_t num_bels_uphill, num_bels_downhill;
RelPtr<BelPortPOD> bels_uphill;
RelPtr<BelPortPOD> bels_downhill;
int32_t num_bel_pins;

2
ice40/arch_place.cc
View File

@ -123,7 +123,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
auto wire = getBelPinWire(iter_bel, portPinFromId(type));
for (auto pip : getPipsDownhill(wire)) {
auto driven_wire = getPipDstWire(pip);
auto io_bel = chip_info->wire_data[driven_wire.index].bel_uphill.bel_index;
auto io_bel = chip_info->wire_data[driven_wire.index].bels_uphill[0].bel_index;
if (io_bel == bel.index) {
return false;
}

2
ice40/bitstream.cc
View File

@ -459,7 +459,7 @@ void write_asc(const Context *ctx, std::ostream &out)
auto wire = ctx->getBelPinWire(cell.second->bel, ctx->portPinFromId(port.second.name));
auto pips = ctx->getPipsDownhill(wire).begin();
auto driven_wire = ctx->getPipDstWire(*pips);
auto io_bel = ctx->chip_info->wire_data[driven_wire.index].bel_uphill.bel_index;
auto io_bel = ctx->chip_info->wire_data[driven_wire.index].bels_uphill[0].bel_index;
auto io_beli = ctx->chip_info->bel_data[io_bel];
NPNR_ASSERT(io_beli.type == TYPE_SB_IO);

30
ice40/chipdb.py
View File

@ -41,7 +41,7 @@ extra_cells = dict()
extra_cell_config = dict()
packages = list()
wire_uphill_belport = dict()
wire_uphill_belports = dict()
wire_downhill_belports = dict()
wire_belports = dict()
@ -462,8 +462,9 @@ def add_bel_input(bel, wire, port):
bel_wires[bel].append((wire, port, 0))
def add_bel_output(bel, wire, port):
assert wire not in wire_uphill_belport
wire_uphill_belport[wire] = (bel, port)
if wire not in wire_uphill_belports:
wire_uphill_belports[wire] = set()
wire_uphill_belports[wire].add((bel, port))
if wire not in wire_belports:
wire_belports[wire] = set()
wire_belports[wire].add((bel, port))
@ -1042,6 +1043,15 @@ for wire in range(num_wires):
num_downhill = 0
list_downhill = None
if wire in wire_uphill_belports:
num_bels_uphill = len(wire_uphill_belports[wire])
bba.l("wire%d_upbels" % wire, "BelPortPOD")
for belport in sorted(wire_uphill_belports[wire]):
bba.u32(belport[0], "bel_index")
bba.u32(portpins[belport[1]], "port")
else:
num_bels_uphill = 0
if wire in wire_downhill_belports:
num_bels_downhill = len(wire_downhill_belports[wire])
bba.l("wire%d_downbels" % wire, "BelPortPOD")
@ -1072,16 +1082,12 @@ for wire in range(num_wires):
info["num_bels_downhill"] = num_bels_downhill
info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None
info["num_bels_uphill"] = num_bels_uphill
info["list_bels_uphill"] = ("wire%d_upbels" % wire) if num_bels_uphill > 0 else None
info["num_bel_pins"] = num_bel_pins
info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None
if wire in wire_uphill_belport:
info["uphill_bel"] = wire_uphill_belport[wire][0]
info["uphill_pin"] = portpins[wire_uphill_belport[wire][1]]
else:
info["uphill_bel"] = -1
info["uphill_pin"] = 0
avg_x, avg_y = 0, 0
if wire in wire_xy:
for x, y in wire_xy[wire]:
@ -1156,9 +1162,9 @@ for wire, info in enumerate(wireinfo):
bba.u32(info["num_downhill"], "num_downhill")
bba.r(info["list_uphill"], "pips_uphill")
bba.r(info["list_downhill"], "pips_downhill")
bba.u32(info["num_bels_uphill"], "num_bels_uphill")
bba.u32(info["num_bels_downhill"], "num_bels_downhill")
bba.u32(info["uphill_bel"], "bel_uphill.bel_index")
bba.u32(info["uphill_pin"], "bel_uphill.port")
bba.r(info["list_bels_uphill"], "bels_uphill")
bba.r(info["list_bels_downhill"], "bels_downhill")
bba.u32(info["num_bel_pins"], "num_bel_pins")
bba.r(info["list_bel_pins"], "bel_pins")