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Merge pull request #247 from YosysHQ/timing-allow-fail

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Add flag timing-allow-fail to allow PnR to pass with warning
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Miodrag Milanović 2019-03-04 13:53:00 +01:00 committed by GitHub
commit 661857fe8e
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2 changed files with 9 additions and 0 deletions
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5
common/command.cc
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@ -129,6 +129,7 @@ po::options_description CommandHandler::getGeneralOptions()
general.add_options()("version,V", "show version"); general.add_options()("version,V", "show version");
general.add_options()("test", "check architecture database integrity"); general.add_options()("test", "check architecture database integrity");
general.add_options()("freq", po::value<double>(), "set target frequency for design in MHz"); general.add_options()("freq", po::value<double>(), "set target frequency for design in MHz");
general.add_options()("timing-allow-fail", "allow timing to fail in design");
general.add_options()("no-tmdriv", "disable timing-driven placement"); general.add_options()("no-tmdriv", "disable timing-driven placement");
general.add_options()("save", po::value<std::string>(), "project file to write"); general.add_options()("save", po::value<std::string>(), "project file to write");
general.add_options()("load", po::value<std::string>(), "project file to read"); general.add_options()("load", po::value<std::string>(), "project file to read");
@ -178,6 +179,10 @@ void CommandHandler::setupContext(Context *ctx)
settings->set("timing/ignoreLoops", true); settings->set("timing/ignoreLoops", true);
} }
if (vm.count("timing-allow-fail")) {
settings->set("timing/allowFail", true);
}
if (vm.count("cstrweight")) { if (vm.count("cstrweight")) {
settings->set("placer1/constraintWeight", vm["cstrweight"].as<float>()); settings->set("placer1/constraintWeight", vm["cstrweight"].as<float>());
} }

4
common/timing.cc
View File

@ -904,6 +904,10 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
if (!warn_on_failure || passed) if (!warn_on_failure || passed)
log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", log_info("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target);
else
if (bool_or_default(ctx->settings, ctx->id("timing/allowFail"), false))
log_warning("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target);
else else
log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "", log_nonfatal_error("Max frequency for clock %*s'%s': %.02f MHz (%s at %.02f MHz)\n", width, "",
clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target); clock_name.c_str(), clock_fmax[clock.first], passed ? "PASS" : "FAIL", target);