Merge pull request #715 from YosysHQ/gatecat/ic-lifcl40

interchange: Add LIFCL-40 EVN tests
This commit is contained in:
gatecat 2021-06-01 11:45:34 +01:00 committed by GitHub
commit 665ab09d20
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12 changed files with 85 additions and 4 deletions

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@ -35,7 +35,7 @@ function get_dependencies {
python3 -m pip install -r requirements.txt
popd
if [ ${DEVICE} == "LIFCL-17" ]; then
if [ ${DEVICE} == "LIFCL-17" ] || [ ${DEVICE} == "LIFCL-40" ]; then
# Install prjoxide
curl --proto '=https' -sSf https://sh.rustup.rs | sh -s -- -y
git clone --recursive https://github.com/gatecat/prjoxide.git

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@ -73,7 +73,7 @@ jobs:
# debugging CI failures.
fail-fast: false
matrix:
device: [xc7a35t, xc7a100t, xc7a200t, xc7z010, LIFCL-17]
device: [xc7a35t, xc7a100t, xc7a200t, xc7z010, LIFCL-17, LIFCL-40]
steps:
- uses: actions/checkout@v2
@ -115,7 +115,7 @@ jobs:
RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
PYTHON_INTERCHANGE_TAG: v0.0.13
PRJOXIDE_REVISION: 7b3e4f85562d3b86a367e8d97d4314ebdee7647a
PRJOXIDE_REVISION: 82b23868d768dac9a5541331e3ddc4c4062627f7
DEVICE: ${{ matrix.device }}
run: |
export PATH="/usr/lib/ccache:/usr/local/opt/ccache/libexec:$PATH"

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@ -40,3 +40,10 @@ add_board(
device LIFCL-17
package QFN72
)
add_board(
name lifcl40evn
device_family nexus
device LIFCL-40
package CABGA400
)

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@ -8,3 +8,4 @@ add_subdirectory(xc7z010)
# Nexus devices
add_subdirectory(LIFCL-17)
add_subdirectory(LIFCL-40)

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@ -0,0 +1,13 @@
generate_nexus_device_db(
device LIFCL-40
device_target lifcl40_target
)
generate_chipdb(
family ${family}
device LIFCL-40
part LIFCL-40-9BG400C
device_target ${lifcl40_target}
device_config ${PYTHON_INTERCHANGE_PATH}/test_data/nexus_device_config.yaml
test_package CABGA400
)

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@ -0,0 +1,8 @@
pip_test:
- src_wire: R3C3_PLC.PLC/JDI0_SLICEA
dst_wire: R3C3/JF0
bel_pin_test:
- bel: R7C3_PLC.PLC/SLICEA_LUT0
pin: D
wire: R7C3_PLC.PLC/JD0_SLICEA

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@ -11,7 +11,7 @@ add_interchange_group_test(
add_interchange_group_test(
name counter
family ${family}
board_list lifcl17
board_list lifcl17 lifcl40evn
tcl run_nexus.tcl
sources counter.v
techmap ../../remap_nexus.v

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@ -0,0 +1,13 @@
set_property PACKAGE_PIN L13 [get_ports clk]
set_property PACKAGE_PIN G19 [get_ports rst]
set_property PACKAGE_PIN E17 [get_ports io_led[4]]
set_property PACKAGE_PIN F13 [get_ports io_led[5]]
set_property PACKAGE_PIN G13 [get_ports io_led[6]]
set_property PACKAGE_PIN F14 [get_ports io_led[7]]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]

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@ -8,3 +8,14 @@ add_interchange_test(
sources lut.v
skip_dcp
)
add_interchange_test(
name lut_nexus40
family ${family}
device LIFCL-40
package CABGA400
tcl run.tcl
xdc empty.xdc
sources lut.v
skip_dcp
)

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@ -6,3 +6,12 @@ add_interchange_group_test(
sources wire.v
output_fasm
)
add_interchange_group_test(
name wire
family ${family}
board_list lifcl40evn
tcl run_nexus.tcl
sources wire.v
skip_dcp
)

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@ -0,0 +1,5 @@
set_property PACKAGE_PIN G19 [get_ports i]
set_property PACKAGE_PIN E17 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i]
set_property IOSTANDARD LVCMOS33 [get_ports o]

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@ -0,0 +1,14 @@
yosys -import
read_verilog $::env(SOURCES)
synth_nexus -nolutram -nowidelut -nobram -noccu2 -nodsp
# opt_expr -undriven makes sure all nets are driven, if only by the $undef
# net.
opt_expr -undriven
opt_clean
setundef -zero -params
write_json $::env(OUT_JSON)