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ice40: Check for SB_IO shared wires conflicts in isValidBelForCell

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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This commit is contained in:
Sylvain Munaut 2019-04-17 14:07:38 +02:00
parent c4cb0c5e49
commit 66b64f928b
1 changed files with 36 additions and 0 deletions
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36
ice40/arch_place.cc
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@ -91,6 +91,18 @@ bool Arch::isBelLocationValid(BelId bel) const
}
}
static inline bool _io_pintype_need_clk_in(unsigned pin_type) { return (pin_type & 0x01) == 0x00; }
static inline bool _io_pintype_need_clk_out(unsigned pin_type)
{
return ((pin_type & 0x30) == 0x30) || ((pin_type & 0x3c) && ((pin_type & 0x0c) != 0x08));
}
static inline bool _io_pintype_need_clk_en(unsigned pin_type)
{
return _io_pintype_need_clk_in(pin_type) || _io_pintype_need_clk_out(pin_type);
}
bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
{
if (cell->type == id_ICESTORM_LC) {
@ -157,6 +169,30 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
CellInfo *compCell = getBoundBelCell(compBel);
if (compCell && compCell->ioInfo.lvds)
return false;
// Check for conflicts on shared nets
// - CLOCK_ENABLE
// - OUTPUT_CLK
// - INPUT_CLK
if (compCell) {
bool use[6] = {
_io_pintype_need_clk_in(cell->ioInfo.pintype),
_io_pintype_need_clk_in(compCell->ioInfo.pintype),
_io_pintype_need_clk_out(cell->ioInfo.pintype),
_io_pintype_need_clk_out(compCell->ioInfo.pintype),
_io_pintype_need_clk_en(cell->ioInfo.pintype),
_io_pintype_need_clk_en(compCell->ioInfo.pintype),
};
NetInfo *nets[] = {
cell->ports[id_INPUT_CLK].net, compCell->ports[id_INPUT_CLK].net,
cell->ports[id_OUTPUT_CLK].net, compCell->ports[id_OUTPUT_CLK].net,
cell->ports[id_CLOCK_ENABLE].net, compCell->ports[id_CLOCK_ENABLE].net,
};
for (int i = 0; i < 6; i++)
if (use[i] && (nets[i] != nets[i ^ 1]) && (use[i ^ 1] || (nets[i ^ 1] != nullptr)))
return false;
}
}
return getBelPackagePin(bel) != "";