ice40: General fixes
Signed-off-by: David Shah <davey1576@gmail.com>
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parent
323a2aaa54
commit
66ea22bb5c
@ -21,6 +21,16 @@
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NEXTPNR_NAMESPACE_BEGIN
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static const NetInfo *
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get_net_or_nullptr(const CellInfo *cell, const IdString port)
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{
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auto found = cell->ports.find(port);
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if (found != cell->ports.end())
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return found->second.net;
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else
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return nullptr;
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};
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static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
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{
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bool dffs_exist = false, dffs_neg = false;
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@ -31,9 +41,9 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
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if (std::stoi(cell->params.at("DFF_ENABLE"))) {
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if (!dffs_exist) {
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dffs_exist = true;
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cen = cell->ports.at("CEN").net;
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clk = cell->ports.at("CLK").net;
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sr = cell->ports.at("SR").net;
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cen = get_net_or_nullptr(cell, "CEN");
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clk = get_net_or_nullptr(cell, "CLK");
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sr = get_net_or_nullptr(cell, "SR");
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locals.insert(cen);
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locals.insert(clk);
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@ -43,21 +53,21 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
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dffs_neg = true;
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}
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} else {
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if (cen != cell->ports.at("CEN").net)
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if (cen != get_net_or_nullptr(cell, "CEN"))
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return false;
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if (clk == cell->ports.at("CLK").net)
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if (clk != get_net_or_nullptr(cell, "CLK"))
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return false;
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if (sr != cell->ports.at("SR").net)
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if (sr != get_net_or_nullptr(cell, "CEN"))
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return false;
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if (dffs_neg != bool(std::stoi(cell->params.at("NEG_CLK"))))
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return false;
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}
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}
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locals.insert(cell->ports.at("I0").net);
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locals.insert(cell->ports.at("I1").net);
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locals.insert(cell->ports.at("I2").net);
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locals.insert(cell->ports.at("I3").net);
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locals.insert(get_net_or_nullptr(cell, "I0"));
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locals.insert(get_net_or_nullptr(cell, "I1"));
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locals.insert(get_net_or_nullptr(cell, "I2"));
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locals.insert(get_net_or_nullptr(cell, "I3"));
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}
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locals.erase(nullptr); // disconnected signals don't use local tracks
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@ -4,6 +4,6 @@ rm -f picorv32.v
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wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
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yosys -p 'synth_ice40 -nocarry -blif picorv32.blif -top top' picorv32.v picorv32_top.v
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arachne-pnr -d 8k --post-place-blif picorv32_place.blif picorv32.blif
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yosys picorv32_place.blif -p "read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json"
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yosys -p "read_blif -wideports picorv32_place.blif; read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json"
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./transform_arachne_loc.py picorv32_place.json > picorv32_place_nx.json
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../nextpnr-ice40 --hx8k --asc picorv32.asc --json picorv32_place_nx.json
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