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ice40: General fixes

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-14 21:12:15 +02:00
parent 323a2aaa54
commit 66ea22bb5c
2 changed files with 21 additions and 11 deletions
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30
ice40/arch_place.cc
View File

@ -21,6 +21,16 @@
NEXTPNR_NAMESPACE_BEGIN NEXTPNR_NAMESPACE_BEGIN
static const NetInfo *
get_net_or_nullptr(const CellInfo *cell, const IdString port)
{
auto found = cell->ports.find(port);
if (found != cell->ports.end())
return found->second.net;
else
return nullptr;
};
static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
{ {
bool dffs_exist = false, dffs_neg = false; bool dffs_exist = false, dffs_neg = false;
@ -31,9 +41,9 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
if (std::stoi(cell->params.at("DFF_ENABLE"))) { if (std::stoi(cell->params.at("DFF_ENABLE"))) {
if (!dffs_exist) { if (!dffs_exist) {
dffs_exist = true; dffs_exist = true;
cen = cell->ports.at("CEN").net; cen = get_net_or_nullptr(cell, "CEN");
clk = cell->ports.at("CLK").net; clk = get_net_or_nullptr(cell, "CLK");
sr = cell->ports.at("SR").net; sr = get_net_or_nullptr(cell, "SR");
locals.insert(cen); locals.insert(cen);
locals.insert(clk); locals.insert(clk);
@ -43,21 +53,21 @@ static bool logicCellsCompatible(const std::vector<const CellInfo *> &cells)
dffs_neg = true; dffs_neg = true;
} }
} else { } else {
if (cen != cell->ports.at("CEN").net) if (cen != get_net_or_nullptr(cell, "CEN"))
return false; return false;
if (clk == cell->ports.at("CLK").net) if (clk != get_net_or_nullptr(cell, "CLK"))
return false; return false;
if (sr != cell->ports.at("SR").net) if (sr != get_net_or_nullptr(cell, "CEN"))
return false; return false;
if (dffs_neg != bool(std::stoi(cell->params.at("NEG_CLK")))) if (dffs_neg != bool(std::stoi(cell->params.at("NEG_CLK"))))
return false; return false;
} }
} }
locals.insert(cell->ports.at("I0").net); locals.insert(get_net_or_nullptr(cell, "I0"));
locals.insert(cell->ports.at("I1").net); locals.insert(get_net_or_nullptr(cell, "I1"));
locals.insert(cell->ports.at("I2").net); locals.insert(get_net_or_nullptr(cell, "I2"));
locals.insert(cell->ports.at("I3").net); locals.insert(get_net_or_nullptr(cell, "I3"));
} }
locals.erase(nullptr); // disconnected signals don't use local tracks locals.erase(nullptr); // disconnected signals don't use local tracks

2
ice40/picorv32_arachne.sh
View File

@ -4,6 +4,6 @@ rm -f picorv32.v
wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v wget https://raw.githubusercontent.com/cliffordwolf/picorv32/master/picorv32.v
yosys -p 'synth_ice40 -nocarry -blif picorv32.blif -top top' picorv32.v picorv32_top.v yosys -p 'synth_ice40 -nocarry -blif picorv32.blif -top top' picorv32.v picorv32_top.v
arachne-pnr -d 8k --post-place-blif picorv32_place.blif picorv32.blif arachne-pnr -d 8k --post-place-blif picorv32_place.blif picorv32.blif
yosys picorv32_place.blif -p "read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json" yosys -p "read_blif -wideports picorv32_place.blif; read_verilog -lib +/ice40/cells_sim.v; write_json picorv32_place.json"
./transform_arachne_loc.py picorv32_place.json > picorv32_place_nx.json ./transform_arachne_loc.py picorv32_place.json > picorv32_place_nx.json
../nextpnr-ice40 --hx8k --asc picorv32.asc --json picorv32_place_nx.json ../nextpnr-ice40 --hx8k --asc picorv32.asc --json picorv32_place_nx.json