Improve estimateDelay for global clocks
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c708a4e0d3
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66f22150b1
@ -232,6 +232,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
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wire_to_tilewire.shrink_to_fit();
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wire_to_tilewire.shrink_to_fit();
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wire_to_delay.shrink_to_fit();
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wire_to_delay.shrink_to_fit();
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num_wires = wire_to_tilewire.size();
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num_wires = wire_to_tilewire.size();
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wire_is_clk.resize(num_wires);
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wire_to_pips_downhill.resize(num_wires);
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wire_to_pips_downhill.resize(num_wires);
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// std::unordered_map<Arc, int> arc_to_pip;
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// std::unordered_map<Arc, int> arc_to_pip;
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@ -256,9 +257,12 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
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auto &pips = wire_to_pips_downhill[w.index];
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auto &pips = wire_to_pips_downhill[w.index];
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pips.reserve(arcs.size());
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pips.reserve(arcs.size());
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const bool clk_tile = boost::starts_with(tileTypeName, "CMT") || boost::starts_with(tileTypeName, "CLK");
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const bool clk_tile = boost::starts_with(tileTypeName, "CLK");
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const bool int_tile = boost::starts_with(tileTypeName, "INT");
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const bool int_tile = boost::starts_with(tileTypeName, "INT");
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if (clk_tile)
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wire_is_clk[w.index] = clk_tile;
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for (const auto &a : arcs) {
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for (const auto &a : arcs) {
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// Disable BUFG I0 -> O routethrough
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// Disable BUFG I0 -> O routethrough
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if (clk_tile) {
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if (clk_tile) {
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@ -324,6 +324,7 @@ struct TorcInfo
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std::vector<WireId> pip_to_dst_wire;
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std::vector<WireId> pip_to_dst_wire;
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int width;
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int width;
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int height;
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int height;
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std::vector<bool> wire_is_clk;
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TorcInfo(const std::string &inDeviceName, const std::string &inPackageName);
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TorcInfo(const std::string &inDeviceName, const std::string &inPackageName);
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private:
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private:
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@ -347,6 +348,7 @@ private:
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ar & pip_to_arc;
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ar & pip_to_arc;
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ar & num_pips;
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ar & num_pips;
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ar & pip_to_dst_wire;
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ar & pip_to_dst_wire;
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ar & wire_is_clk;
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}
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}
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};
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};
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extern std::unique_ptr<const TorcInfo> torc_info;
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extern std::unique_ptr<const TorcInfo> torc_info;
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11
xc7/delay.cc
11
xc7/delay.cc
@ -104,6 +104,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex());
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const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex());
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const auto &dst_tw = torc_info->wire_to_tilewire[dst.index];
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const auto &dst_tw = torc_info->wire_to_tilewire[dst.index];
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const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
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const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
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if (!torc_info->wire_is_clk[src.index]) {
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auto abs_delta_x = abs(src_info.getCol() - dst_info.getCol());
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auto abs_delta_x = abs(src_info.getCol() - dst_info.getCol());
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auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow());
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auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow());
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#if 1
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#if 1
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@ -125,6 +127,15 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
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return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
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#endif
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#endif
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}
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}
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else {
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auto src_y = src_info.getRow();
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auto dst_y = dst_info.getRow();
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src_y -= src_y % 50;
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dst_y -= dst_y % 50;
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auto abs_delta_y = abs(src_y - dst_y);
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return abs_delta_y * 64; // arbitrary factor
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}
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}
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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{
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{
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