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Improve estimateDelay for global clocks

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This commit is contained in:
Eddie Hung 2018-12-06 16:49:35 -08:00
parent c708a4e0d3
commit 66f22150b1
3 changed files with 35 additions and 18 deletions
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6
xc7/arch.cc
View File

@ -232,6 +232,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
wire_to_tilewire.shrink_to_fit();
wire_to_delay.shrink_to_fit();
num_wires = wire_to_tilewire.size();
wire_is_clk.resize(num_wires);
wire_to_pips_downhill.resize(num_wires);
// std::unordered_map<Arc, int> arc_to_pip;
@ -256,9 +257,12 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
auto &pips = wire_to_pips_downhill[w.index];
pips.reserve(arcs.size());
const bool clk_tile = boost::starts_with(tileTypeName, "CMT") || boost::starts_with(tileTypeName, "CLK");
const bool clk_tile = boost::starts_with(tileTypeName, "CLK");
const bool int_tile = boost::starts_with(tileTypeName, "INT");
if (clk_tile)
wire_is_clk[w.index] = clk_tile;
for (const auto &a : arcs) {
// Disable BUFG I0 -> O routethrough
if (clk_tile) {

2
xc7/arch.h
View File

@ -324,6 +324,7 @@ struct TorcInfo
std::vector<WireId> pip_to_dst_wire;
int width;
int height;
std::vector<bool> wire_is_clk;
TorcInfo(const std::string &inDeviceName, const std::string &inPackageName);
private:
@ -347,6 +348,7 @@ private:
ar & pip_to_arc;
ar & num_pips;
ar & pip_to_dst_wire;
ar & wire_is_clk;
}
};
extern std::unique_ptr<const TorcInfo> torc_info;

11
xc7/delay.cc
View File

@ -104,6 +104,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex());
const auto &dst_tw = torc_info->wire_to_tilewire[dst.index];
const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
if (!torc_info->wire_is_clk[src.index]) {
auto abs_delta_x = abs(src_info.getCol() - dst_info.getCol());
auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow());
#if 1
@ -124,6 +126,15 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
#else
return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
#endif
}
else {
auto src_y = src_info.getRow();
auto dst_y = dst_info.getRow();
src_y -= src_y % 50;
dst_y -= dst_y % 50;
auto abs_delta_y = abs(src_y - dst_y);
return abs_delta_y * 64; // arbitrary factor
}
}
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const