ice40: Add support for LC placement constraints in packer
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
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a139654980
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@ -75,7 +75,7 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX IdString>
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return std::hash<std::string>()(obj.data);
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return std::hash<std::string>()(obj.data);
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}
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}
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};
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};
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}
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} // namespace std
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NEXTPNR_NAMESPACE_BEGIN
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NEXTPNR_NAMESPACE_BEGIN
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@ -19,12 +19,12 @@
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*/
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*/
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#include "pack.h"
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#include "pack.h"
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#include <algorithm>
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#include <unordered_set>
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#include "cells.h"
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#include "cells.h"
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#include "design_utils.h"
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#include "design_utils.h"
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#include "log.h"
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#include "log.h"
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#include <unordered_set>
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NEXTPNR_NAMESPACE_BEGIN
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NEXTPNR_NAMESPACE_BEGIN
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// Pack LUTs and LUT-FF pairs
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// Pack LUTs and LUT-FF pairs
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@ -39,6 +39,8 @@ static void pack_lut_lutffs(Design *design)
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if (is_lut(ci)) {
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if (is_lut(ci)) {
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CellInfo *packed = create_ice_cell(design, "ICESTORM_LC",
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CellInfo *packed = create_ice_cell(design, "ICESTORM_LC",
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ci->name.str() + "_LC");
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ci->name.str() + "_LC");
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std::copy(ci->attrs.begin(), ci->attrs.end(),
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std::inserter(packed->attrs, packed->attrs.begin()));
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packed_cells.insert(ci->name);
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packed_cells.insert(ci->name);
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new_cells.push_back(packed);
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new_cells.push_back(packed);
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log_info("packed cell %s into %s\n", ci->name.c_str(),
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log_info("packed cell %s into %s\n", ci->name.c_str(),
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@ -47,14 +49,26 @@ static void pack_lut_lutffs(Design *design)
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// TODO: LUT cascade
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// TODO: LUT cascade
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NetInfo *o = ci->ports.at("O").net;
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NetInfo *o = ci->ports.at("O").net;
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CellInfo *dff = net_only_drives(o, is_ff, "D", true);
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CellInfo *dff = net_only_drives(o, is_ff, "D", true);
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auto lut_bel = ci->attrs.find("BEL");
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bool packed_dff = false;
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if (dff) {
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if (dff) {
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auto dff_bel = dff->attrs.find("BEL");
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if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() &&
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lut_bel->second != dff_bel->second) {
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// Locations don't match, can't pack
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} else {
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lut_to_lc(ci, packed, false);
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lut_to_lc(ci, packed, false);
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dff_to_lc(dff, packed, false);
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dff_to_lc(dff, packed, false);
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design->nets.erase(o->name);
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design->nets.erase(o->name);
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if (dff_bel != dff->attrs.end())
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packed->attrs["BEL"] = dff_bel->second;
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packed_cells.insert(dff->name);
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packed_cells.insert(dff->name);
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log_info("packed cell %s into %s\n", dff->name.c_str(),
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log_info("packed cell %s into %s\n", dff->name.c_str(),
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packed->name.c_str());
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packed->name.c_str());
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} else {
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packed_dff = true;
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}
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}
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if (!packed_dff) {
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lut_to_lc(ci, packed, true);
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lut_to_lc(ci, packed, true);
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}
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}
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}
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}
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@ -78,6 +92,8 @@ static void pack_nonlut_ffs(Design *design)
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if (is_ff(ci)) {
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if (is_ff(ci)) {
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CellInfo *packed = create_ice_cell(design, "ICESTORM_LC",
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CellInfo *packed = create_ice_cell(design, "ICESTORM_LC",
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ci->name.str() + "_LC");
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ci->name.str() + "_LC");
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std::copy(ci->attrs.begin(), ci->attrs.end(),
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std::inserter(packed->attrs, packed->attrs.begin()));
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packed_cells.insert(ci->name);
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packed_cells.insert(ci->name);
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new_cells.push_back(packed);
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new_cells.push_back(packed);
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dff_to_lc(ci, packed, true);
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dff_to_lc(ci, packed, true);
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54
ice40/pack_tests/place_constr.v
Normal file
54
ice40/pack_tests/place_constr.v
Normal file
@ -0,0 +1,54 @@
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module top(input clk, cen, rst, ina, inb, output outa, outb, outc, outd);
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wire temp0, temp1;
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(* BEL="1_1_lc0" *)
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SB_LUT4 #(
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.LUT_INIT(2'b01)
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) lut0 (
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.I3(),
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.I2(),
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.I1(),
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.I0(ina),
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.O(temp0)
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);
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(* BEL="1_3_lc0" *)
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SB_LUT4 #(
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.LUT_INIT(2'b01)
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) lut1 (
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.I3(),
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.I2(),
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.I1(),
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.I0(inb),
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.O(temp1)
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);
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(* BEL="1_1_lc0" *)
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SB_DFF ff0 (
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.C(clk),
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.D(temp1),
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.Q(outa)
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);
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(* BEL="1_1_lc7" *)
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SB_DFF ff1 (
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.C(clk),
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.D(inb),
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.Q(outb)
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);
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(* BEL="1_6_lc7" *)
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SB_DFF ff2 (
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.C(clk),
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.D(temp1),
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.Q(outc)
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);
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assign outd = 1'b0;
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endmodule
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@ -5,7 +5,8 @@ yosys -p "synth_ice40 -nocarry -top io_wrapper; write_json ${NAME}.json" $1 io_w
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../../nextpnr-ice40 --json ${NAME}.json --pack --asc ${NAME}.asc
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../../nextpnr-ice40 --json ${NAME}.json --pack --asc ${NAME}.asc
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icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
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icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
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yosys -p "rename chip gate;\
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yosys -p "read_verilog +/ice40/cells_sim.v;\
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rename chip gate;\
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read_verilog $1;\
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read_verilog $1;\
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rename top gold;\
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rename top gold;\
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hierarchy;\
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hierarchy;\
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