From 67a0fa11e673015c252f9c8fe655c95f69ea53a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sat, 11 Aug 2018 21:36:23 -0700
Subject: [PATCH] Enable timing

---
 xc7/arch.cc      | 39 ++++++++++++++++++++++++++++++++++++---
 xc7/cells.h      |  2 +-
 xc7/constids.inc |  7 ++++++-
 3 files changed, 43 insertions(+), 5 deletions(-)

diff --git a/xc7/arch.cc b/xc7/arch.cc
index fd0eb6bd..7202d1cc 100644
--- a/xc7/arch.cc
+++ b/xc7/arch.cc
@@ -677,14 +677,47 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
 // Get the port class, also setting clockPort to associated clock if applicable
 TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
 {
-    return TMG_IGNORE;
+    if (cell->type == id_SLICEL) {
+        if (port == id_CLK)
+            return TMG_CLOCK_INPUT;
+        if (port == id_CIN)
+            return TMG_COMB_INPUT;
+        if (port == id_COUT || port == id_O)
+            return TMG_COMB_OUTPUT;
+        if (cell->lcInfo.dffEnable) {
+            clockPort = id_CLK;
+            if (port == id_OQ)
+                return TMG_REGISTER_OUTPUT;
+            else
+                return TMG_REGISTER_INPUT;
+        } else {
+            if (port == id_O)
+                return TMG_COMB_OUTPUT;
+            else
+                return TMG_COMB_INPUT;
+        }
+        // TODO
+        //if (port == id_OMUX)
+    }
+    else if (cell->type == id_IOB33S) {
+        if (port == id_I)
+            return TMG_STARTPOINT;
+        else if (port == id_O)
+            return TMG_ENDPOINT;
+    }
+    else if (cell->type == id_BUFGCTRL) {
+        if (port == id_O)
+            return TMG_COMB_OUTPUT;
+        return TMG_COMB_INPUT;
+    }
+    log_error("no timing info for port '%s' of cell type '%s'\n", port.c_str(this), cell->type.c_str(this));
 }
 
 bool Arch::isGlobalNet(const NetInfo *net) const
 {
     if (net == nullptr)
         return false;
-    return net->driver.cell != nullptr && net->driver.port == id_GLOBAL_BUFFER_OUTPUT;
+    return net->driver.cell != nullptr && net->driver.cell->type == id_BUFGCTRL && net->driver.port == id_O;
 }
 
 // Assign arch arg info
@@ -712,7 +745,7 @@ void Arch::assignArchInfo()
 void Arch::assignCellInfo(CellInfo *cell)
 {
     cell->belType = cell->type;
-    if (cell->type == id_ICESTORM_LC) {
+    if (cell->type == id_SLICEL) {
         cell->lcInfo.dffEnable = bool_or_default(cell->params, id_DFF_ENABLE);
         cell->lcInfo.carryEnable = bool_or_default(cell->params, id_CARRY_ENABLE);
         cell->lcInfo.negClk = bool_or_default(cell->params, id_NEG_CLK);
diff --git a/xc7/cells.h b/xc7/cells.h
index 2a1d8f90..3f671f2a 100644
--- a/xc7/cells.h
+++ b/xc7/cells.h
@@ -46,7 +46,7 @@ inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type
 inline bool is_sb_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("SB_IO"); }
 
 // Return true if a cell is a global buffer
-inline bool is_gbuf(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("BUFGCTRL"); }
+inline bool is_gbuf(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_BUFGCTRL; }
 
 // Return true if a cell is a RAM
 inline bool is_ram(const BaseCtx *ctx, const CellInfo *cell)
diff --git a/xc7/constids.inc b/xc7/constids.inc
index 10543fb3..6dd7da6c 100644
--- a/xc7/constids.inc
+++ b/xc7/constids.inc
@@ -3,8 +3,11 @@ X(I0)
 X(I1)
 X(I2)
 X(I3)
+X(I4)
+X(I5)
 X(O)
-X(LO)
+X(OQ)
+X(OMUX)
 X(CIN)
 X(COUT)
 X(CEN)
@@ -436,6 +439,8 @@ X(DFF_ENABLE)
 X(CARRY_ENABLE)
 X(NEG_CLK)
 
+X(I)
+
 X(LUT1)
 X(LUT2)
 X(LUT3)