From 67a5cedbe30f681fd3c5c52ed8552abcc7583a45 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 12 Jun 2018 13:09:36 +0200 Subject: [PATCH] ice40: Pack constants to LCs Signed-off-by: David Shah --- ice40/blinky_nopack.ys | 2 +- ice40/blinky_noyspack.sh | 8 ++++++++ ice40/icebreaker.ys | 8 +------- ice40/pack.cc | 25 +++++++++++++++++++++++++ 4 files changed, 35 insertions(+), 8 deletions(-) create mode 100755 ice40/blinky_noyspack.sh diff --git a/ice40/blinky_nopack.ys b/ice40/blinky_nopack.ys index 2fea95bc..aeaa518b 100644 --- a/ice40/blinky_nopack.ys +++ b/ice40/blinky_nopack.ys @@ -1,3 +1,3 @@ read_verilog blinky.v synth_ice40 -nocarry -top blinky -write_json blinky.json +write_json blinky_nopack.json diff --git a/ice40/blinky_noyspack.sh b/ice40/blinky_noyspack.sh new file mode 100755 index 00000000..00824ae9 --- /dev/null +++ b/ice40/blinky_noyspack.sh @@ -0,0 +1,8 @@ +#!/bin/bash +set -ex +yosys blinky_nopack.ys +../nextpnr-ice40 --json blinky_nopack.json --asc blinky.asc --pack +icepack blinky.asc blinky.bin +icebox_vlog blinky.asc > blinky_chip.v +iverilog -o blinky_tb blinky_chip.v blinky_tb.v +vvp -N ./blinky_tb diff --git a/ice40/icebreaker.ys b/ice40/icebreaker.ys index 7933254d..878914aa 100644 --- a/ice40/icebreaker.ys +++ b/ice40/icebreaker.ys @@ -1,9 +1,3 @@ read_verilog icebreaker.v -read_verilog -lib +/ice40/cells_sim.v -synth -top icebreaker -abc -lut 4 -techmap -map blinky_map.v -splitnets -opt_clean -stat +synth_ice40 -nocarry -top icebreaker write_json icebreaker.json diff --git a/ice40/pack.cc b/ice40/pack.cc index 47e55b68..eb783f2f 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -89,9 +89,34 @@ static void pack_nonlut_ffs(Design *design) } } +// Pack constants (simple implementation) +static void pack_constants(Design *design) { + CellInfo *gnd_cell = create_ice_cell(design, "ICESTORM_LC", + "$PACKER_GND"); + gnd_cell->attrs["LUT_INIT"] = "0"; + + CellInfo *vcc_cell = create_ice_cell(design, "ICESTORM_LC", + "$PACKER_VCC"); + vcc_cell->attrs["LUT_INIT"] = "1"; + + for (auto net : design->nets) { + NetInfo *ni = net.second; + if (ni->driver.cell != nullptr && ni->driver.cell->type == "GND") { + ni->driver.cell = gnd_cell; + ni->driver.port = "O"; + design->cells[gnd_cell->name] = gnd_cell; + } else if (ni->driver.cell != nullptr && ni->driver.cell->type == "VCC") { + ni->driver.cell = vcc_cell; + ni->driver.port = "O"; + design->cells[vcc_cell->name] = vcc_cell; + } + } +} + // Main pack function void pack_design(Design *design) { + pack_constants(design); pack_lut_lutffs(design); pack_nonlut_ffs(design); }