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Address review comments.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-01-28 09:28:40 -08:00
parent 5a89dc58e1
commit 67dc19bb57
3 changed files with 6 additions and 95 deletions
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13
fpga_interchange/arch.cc
View File

@ -177,13 +177,10 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const
NPNR_ASSERT(bel != BelId());
int pin_index = getBelPinIndex(bel, pin);
if(pin_index < 0) {
// Port could not be found!
return PORT_INOUT;
} else {
const int32_t *types = locInfo(bel).bel_data[bel.index].types.get();
return PortType(types[pin_index]);
}
auto &bel_data = locInfo(bel).bel_data[bel.index];
NPNR_ASSERT(pin_index >= 0 && pin_index < bel_data.num_bel_wires);
const int32_t *types = bel_data.types.get();
return PortType(types[pin_index]);
}
// -----------------------------------------------------------------------
@ -464,7 +461,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
delay_t Arch::estimateDelay(WireId src, WireId dst, bool debug) const
{
// FIXME: Implement when adding timing-driven place and route.
// FIXME: Implement something to push the A* router in the right direction.
return 0;
}

1
fpga_interchange/arch.h
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@ -1028,6 +1028,7 @@ struct Arch : BaseCtx
// -------------------------------------------------
// TODO: Use groups to get access to sites.
GroupId getGroupByName(IdString name) const { return GroupId(); }
IdString getGroupName(GroupId group) const { return IdString(); }
std::vector<GroupId> getGroups() const { return {}; }

87
fpga_interchange/fpga_interchange_archdefs.h
View File

@ -1,87 +0,0 @@
#include <cstdint>
typedef int delay_t;
struct DelayInfo
{
delay_t delay = 0;
delay_t minRaiseDelay() const { return delay; }
delay_t maxRaiseDelay() const { return delay; }
delay_t minFallDelay() const { return delay; }
delay_t maxFallDelay() const { return delay; }
delay_t minDelay() const { return delay; }
delay_t maxDelay() const { return delay; }
DelayInfo operator+(const DelayInfo &other) const
{
DelayInfo ret;
ret.delay = this->delay + other.delay;
return ret;
}
};
struct BelId
{
// Tile that contains this BEL.
int32_t tile = -1;
// Index into tile type BEL array.
// BEL indicies are the same for all tiles of the same type.
int32_t index = -1;
bool operator==(const BelId &other) const { return tile == other.tile && index == other.index; }
bool operator!=(const BelId &other) const { return tile != other.tile || index != other.index; }
bool operator<(const BelId &other) const
{
return tile < other.tile || (tile == other.tile && index < other.index);
}
};
struct WireId
{
// Tile that contains this wire.
int32_t tile = -1;
int32_t index = -1;
bool operator==(const WireId &other) const { return tile == other.tile && index == other.index; }
bool operator!=(const WireId &other) const { return tile != other.tile || index != other.index; }
bool operator<(const WireId &other) const
{
return tile < other.tile || (tile == other.tile && index < other.index);
}
};
struct PipId
{
int32_t tile = -1;
int32_t index = -1;
bool operator==(const PipId &other) const { return tile == other.tile && index == other.index; }
bool operator!=(const PipId &other) const { return tile != other.tile || index != other.index; }
bool operator<(const PipId &other) const
{
return tile < other.tile || (tile == other.tile && index < other.index);
}
};
struct GroupId
{
};
struct DecalId
{
};
struct ArchNetInfo
{
};
struct NetInfo
{
};
struct ArchCellInfo
{
};