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Add iCE40 SB_IO bels

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-03 16:16:59 +02:00
parent d41936ecbf
commit 6840ffd9c0
3 changed files with 106 additions and 26 deletions
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84
ice40/chip.cc
View File

@ -23,13 +23,19 @@
IdString belTypeToId(BelType type)
{
if (type == TYPE_ICESTORM_LC) return "ICESTORM_LC";
if (type == TYPE_ICESTORM_LC)
return "ICESTORM_LC";
if (type == TYPE_SB_IO)
return "SB_IO";
return IdString();
}
BelType belTypeFromId(IdString id)
{
if (id == "ICESTORM_LC") return TYPE_ICESTORM_LC;
if (id == "ICESTORM_LC")
return TYPE_ICESTORM_LC;
if (id == "SB_IO")
return TYPE_SB_IO;
return TYPE_NIL;
}
@ -37,33 +43,63 @@ BelType belTypeFromId(IdString id)
IdString PortPinToId(PortPin type)
{
if (type == PIN_IN_0) return "IN_0";
if (type == PIN_IN_1) return "IN_1";
if (type == PIN_IN_2) return "IN_2";
if (type == PIN_IN_3) return "IN_3";
if (type == PIN_O ) return "O";
if (type == PIN_LO ) return "LO";
if (type == PIN_CIN ) return "CIN";
if (type == PIN_COUT) return "COUT";
if (type == PIN_CEN ) return "CEN";
if (type == PIN_CLK ) return "CLK";
if (type == PIN_SR ) return "SR";
#define X(t) if (type == PIN_##t) return #t;
X(IN_0)
X(IN_1)
X(IN_2)
X(IN_3)
X(O)
X(LO)
X(CIN)
X(COUT)
X(CEN)
X(CLK)
X(SR)
X(PACKAGE_PIN)
X(LATCH_INPUT_VALUE)
X(CLOCK_ENABLE)
X(INPUT_CLK)
X(OUTPUT_CLK)
X(OUTPUT_ENABLE)
X(D_OUT_0)
X(D_OUT_1)
X(D_IN_0)
X(D_IN_1)
#undef X
return IdString();
}
PortPin PortPinFromId(IdString id)
{
if (id == "IN_0") return PIN_IN_0;
if (id == "IN_1") return PIN_IN_1;
if (id == "IN_2") return PIN_IN_2;
if (id == "IN_3") return PIN_IN_3;
if (id == "O" ) return PIN_O;
if (id == "LO" ) return PIN_LO;
if (id == "CIN" ) return PIN_CIN;
if (id == "COUT") return PIN_COUT;
if (id == "CEN" ) return PIN_CEN;
if (id == "CLK" ) return PIN_CLK;
if (id == "SR" ) return PIN_SR;
#define X(t) if (id == #t) return PIN_##t;
X(IN_0)
X(IN_1)
X(IN_2)
X(IN_3)
X(O)
X(LO)
X(CIN)
X(COUT)
X(CEN)
X(CLK)
X(SR)
X(PACKAGE_PIN)
X(LATCH_INPUT_VALUE)
X(CLOCK_ENABLE)
X(INPUT_CLK)
X(OUTPUT_CLK)
X(OUTPUT_ENABLE)
X(D_OUT_0)
X(D_OUT_1)
X(D_IN_0)
X(D_IN_1)
#undef X
return PIN_NIL;
}

17
ice40/chip.h
View File

@ -35,7 +35,8 @@ struct DelayInfo
enum BelType
{
TYPE_NIL,
TYPE_ICESTORM_LC
TYPE_ICESTORM_LC,
TYPE_SB_IO
};
IdString belTypeToId(BelType type);
@ -44,6 +45,7 @@ BelType belTypeFromId(IdString id);
enum PortPin
{
PIN_NIL,
PIN_IN_0,
PIN_IN_1,
PIN_IN_2,
@ -54,7 +56,18 @@ enum PortPin
PIN_COUT,
PIN_CEN,
PIN_CLK,
PIN_SR
PIN_SR,
PIN_PACKAGE_PIN,
PIN_LATCH_INPUT_VALUE,
PIN_CLOCK_ENABLE,
PIN_INPUT_CLK,
PIN_OUTPUT_CLK,
PIN_OUTPUT_ENABLE,
PIN_D_OUT_0,
PIN_D_OUT_1,
PIN_D_IN_0,
PIN_D_IN_1
};
IdString PortPinToId(PortPin type);

31
ice40/chipdb.py
View File

@ -153,10 +153,41 @@ def add_bel_lc(x, y, z):
if wire_lout is not None:
add_bel_output(bel, wire_lout, "LO")
def add_bel_io(x, y, z):
bel = len(bel_name)
bel_name.append("%d_%d_lc%d" % (x, y, z))
bel_type.append("SB_IO")
wire_cen = wire_names[(x, y, "io_global/cen")]
wire_iclk = wire_names[(x, y, "io_global/inclk")]
wire_oclk = wire_names[(x, y, "io_global/latch")]
wire_latch = wire_names[(x, y, "io_global/outclk")]
wire_din_0 = wire_names[(x, y, "io_%d/D_IN_0" % z)]
wire_din_1 = wire_names[(x, y, "io_%d/D_IN_1" % z)]
wire_dout_0 = wire_names[(x, y, "io_%d/D_OUT_0" % z)]
wire_dout_1 = wire_names[(x, y, "io_%d/D_OUT_1" % z)]
wire_out_en = wire_names[(x, y, "io_%d/OUT_ENB" % z)]
add_bel_input(bel, wire_cen, "CLOCK_ENABLE")
add_bel_input(bel, wire_iclk, "INPUT_CLK")
add_bel_input(bel, wire_oclk, "OUTPUT_CLK")
add_bel_input(bel, wire_latch, "LATCH_INPUT_VALUE")
add_bel_output(bel, wire_din_0, "D_IN_0")
add_bel_output(bel, wire_din_1, "D_IN_1")
add_bel_input(bel, wire_dout_0, "D_OUT_0")
add_bel_input(bel, wire_dout_1, "D_OUT_1")
add_bel_input(bel, wire_out_en, "OUTPUT_ENABLE")
for tile_xy, tile_type in sorted(tiles.items()):
if tile_type == "logic":
for i in range(8):
add_bel_lc(tile_xy[0], tile_xy[1], i)
if tile_type == "io":
for i in range(2):
add_bel_io(tile_xy[0], tile_xy[1], i)
print('#include "chip.h"')