Add iCE40 SB_IO bels

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ice40/chip.cc

@@ -23,13 +23,19 @@
 
 IdString belTypeToId(BelType type)
 {
-	if (type == TYPE_ICESTORM_LC) return "ICESTORM_LC";
+	if (type == TYPE_ICESTORM_LC)
+		return "ICESTORM_LC";
+	if (type == TYPE_SB_IO)
+		return "SB_IO";
 	return IdString();
 }
 
 BelType belTypeFromId(IdString id)
 {
-	if (id == "ICESTORM_LC") return TYPE_ICESTORM_LC;
+	if (id == "ICESTORM_LC")
+		return TYPE_ICESTORM_LC;
+	if (id == "SB_IO")
+		return TYPE_SB_IO;
 	return TYPE_NIL;
 }
 
@@ -37,33 +43,63 @@ BelType belTypeFromId(IdString id)
 
 IdString PortPinToId(PortPin type)
 {
-	if (type == PIN_IN_0) return "IN_0";
+#define X(t) if (type == PIN_##t) return #t;
-	if (type == PIN_IN_1) return "IN_1";
+
-	if (type == PIN_IN_2) return "IN_2";
+	X(IN_0)
-	if (type == PIN_IN_3) return "IN_3";
+	X(IN_1)
-	if (type == PIN_O   ) return "O";
+	X(IN_2)
-	if (type == PIN_LO  ) return "LO";
+	X(IN_3)
-	if (type == PIN_CIN ) return "CIN";
+	X(O)
-	if (type == PIN_COUT) return "COUT";
+	X(LO)
-	if (type == PIN_CEN ) return "CEN";
+	X(CIN)
-	if (type == PIN_CLK ) return "CLK";
+	X(COUT)
-	if (type == PIN_SR  ) return "SR";
+	X(CEN)
+	X(CLK)
+	X(SR)
+
+	X(PACKAGE_PIN)
+	X(LATCH_INPUT_VALUE)
+	X(CLOCK_ENABLE)
+	X(INPUT_CLK)
+	X(OUTPUT_CLK)
+	X(OUTPUT_ENABLE)
+	X(D_OUT_0)
+	X(D_OUT_1)
+	X(D_IN_0)
+	X(D_IN_1)
+
+#undef X
 	return IdString();
 }
 
 PortPin PortPinFromId(IdString id)
 {
-	if (id == "IN_0") return PIN_IN_0;
+#define X(t) if (id == #t) return PIN_##t;
-	if (id == "IN_1") return PIN_IN_1;
+
-	if (id == "IN_2") return PIN_IN_2;
+	X(IN_0)
-	if (id == "IN_3") return PIN_IN_3;
+	X(IN_1)
-	if (id == "O"   ) return PIN_O;
+	X(IN_2)
-	if (id == "LO"  ) return PIN_LO;
+	X(IN_3)
-	if (id == "CIN" ) return PIN_CIN;
+	X(O)
-	if (id == "COUT") return PIN_COUT;
+	X(LO)
-	if (id == "CEN" ) return PIN_CEN;
+	X(CIN)
-	if (id == "CLK" ) return PIN_CLK;
+	X(COUT)
-	if (id == "SR"  ) return PIN_SR;
+	X(CEN)
+	X(CLK)
+	X(SR)
+
+	X(PACKAGE_PIN)
+	X(LATCH_INPUT_VALUE)
+	X(CLOCK_ENABLE)
+	X(INPUT_CLK)
+	X(OUTPUT_CLK)
+	X(OUTPUT_ENABLE)
+	X(D_OUT_0)
+	X(D_OUT_1)
+	X(D_IN_0)
+	X(D_IN_1)
+
+#undef X
 	return PIN_NIL;
 }
 

ice40/chip.h

@@ -35,7 +35,8 @@ struct DelayInfo
 enum BelType
 {
 	TYPE_NIL,
-	TYPE_ICESTORM_LC
+	TYPE_ICESTORM_LC,
+	TYPE_SB_IO
 };
 
 IdString belTypeToId(BelType type);
@@ -44,6 +45,7 @@ BelType belTypeFromId(IdString id);
 enum PortPin
 {
 	PIN_NIL,
+
 	PIN_IN_0,
 	PIN_IN_1,
 	PIN_IN_2,
@@ -54,7 +56,18 @@ enum PortPin
 	PIN_COUT,
 	PIN_CEN,
 	PIN_CLK,
-	PIN_SR
+	PIN_SR,
+
+	PIN_PACKAGE_PIN,
+	PIN_LATCH_INPUT_VALUE,
+	PIN_CLOCK_ENABLE,
+	PIN_INPUT_CLK,
+	PIN_OUTPUT_CLK,
+	PIN_OUTPUT_ENABLE,
+	PIN_D_OUT_0,
+	PIN_D_OUT_1,
+	PIN_D_IN_0,
+	PIN_D_IN_1
 };
 
 IdString PortPinToId(PortPin type);

ice40/chipdb.py

@@ -153,10 +153,41 @@ def add_bel_lc(x, y, z):
     if wire_lout is not None:
         add_bel_output(bel, wire_lout, "LO")
 
+def add_bel_io(x, y, z):
+    bel = len(bel_name)
+    bel_name.append("%d_%d_lc%d" % (x, y, z))
+    bel_type.append("SB_IO")
+
+    wire_cen   = wire_names[(x, y, "io_global/cen")]
+    wire_iclk  = wire_names[(x, y, "io_global/inclk")]
+    wire_oclk  = wire_names[(x, y, "io_global/latch")]
+    wire_latch = wire_names[(x, y, "io_global/outclk")]
+
+    wire_din_0  = wire_names[(x, y, "io_%d/D_IN_0"  % z)]
+    wire_din_1  = wire_names[(x, y, "io_%d/D_IN_1"  % z)]
+    wire_dout_0 = wire_names[(x, y, "io_%d/D_OUT_0" % z)]
+    wire_dout_1 = wire_names[(x, y, "io_%d/D_OUT_1" % z)]
+    wire_out_en = wire_names[(x, y, "io_%d/OUT_ENB" % z)]
+
+    add_bel_input(bel, wire_cen,    "CLOCK_ENABLE")
+    add_bel_input(bel, wire_iclk,   "INPUT_CLK")
+    add_bel_input(bel, wire_oclk,   "OUTPUT_CLK")
+    add_bel_input(bel, wire_latch,  "LATCH_INPUT_VALUE")
+
+    add_bel_output(bel, wire_din_0, "D_IN_0")
+    add_bel_output(bel, wire_din_1, "D_IN_1")
+
+    add_bel_input(bel, wire_dout_0, "D_OUT_0")
+    add_bel_input(bel, wire_dout_1, "D_OUT_1")
+    add_bel_input(bel, wire_out_en, "OUTPUT_ENABLE")
+
 for tile_xy, tile_type in sorted(tiles.items()):
     if tile_type == "logic":
         for i in range(8):
             add_bel_lc(tile_xy[0], tile_xy[1], i)
+    if tile_type == "io":
+        for i in range(2):
+            add_bel_io(tile_xy[0], tile_xy[1], i)
 
 print('#include "chip.h"')