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Progress with chipdb refactoring

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-16 19:25:37 +02:00
parent ee06db3293
commit 69e5bc5030
4 changed files with 39 additions and 23 deletions
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2
ice40/bitstream.cc
View File

@ -31,7 +31,7 @@ const ConfigEntryPOD &find_config(const TileInfoPOD &tile,
const std::string &name)
{
for (int i = 0; i < tile.num_config_entries; i++) {
if (std::string(tile.entries[i].name) == name) {
if (std::string(tile.entries[i].name.ptr()) == name) {
return tile.entries[i];
}
}

2
ice40/chip.cc
View File

@ -190,7 +190,7 @@ WireId Chip::getWireBelPin(BelId bel, PortPin pin) const
assert(bel != BelId());
int num_bel_wires = chip_info.bel_data[bel.index].num_bel_wires;
BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires.ptr();
const BelWirePOD *bel_wires = chip_info.bel_data[bel.index].bel_wires.ptr();
for (int i = 0; i < num_bel_wires; i++)
if (bel_wires[i].port == pin) {

24
ice40/chip.h
View File

@ -76,19 +76,23 @@ template <typename T>
struct RelPtr {
int offset;
// RelPtr(T *ptr) : offset(reinterpret_cast<const char*>(ptr) -
// RelPtr(const T *ptr) : offset(reinterpret_cast<const char*>(ptr) -
// reinterpret_cast<const char*>(this)) {}
T&operator*() {
return *reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
const T&operator[](size_t index) const {
return reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset)[index];
}
T*operator->() {
return reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
const T&operator*() const {
return *reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset);
}
T*ptr() {
return reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
const T*operator->() const {
return reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset);
}
const T*ptr() const {
return reinterpret_cast<const T*>(reinterpret_cast<const char*>(this) + offset);
}
};
@ -165,9 +169,9 @@ struct ConfigBitPOD
struct ConfigEntryPOD
{
const char *name;
int num_bits;
ConfigBitPOD *bits;
RelPtr<char> name;
int32_t num_bits;
RelPtr<ConfigBitPOD> bits;
} __attribute__((packed));
struct TileInfoPOD

32
ice40/chipdb.py
View File

@ -594,10 +594,6 @@ for package in packages:
bba.u32(pi[1], "bel_index")
packageinfo.append('{"%s", %d, package_%s_pins}' % (name, len(pins_info), safename))
print("static uint8_t binblob_%s[] = {" % dev_name)
bba.write_c(sys.stdout)
print("};")
tilegrid = []
for y in range(dev_height):
for x in range(dev_width):
@ -612,14 +608,30 @@ for t in range(num_tile_types):
for cb in tile_bits[t]:
name, bits = cb
safename = re.sub("[^A-Za-z0-9]", "_", name)
bits_list = ["{%d, %d}" % _ for _ in bits]
print("static ConfigBitPOD tile%d_%s_bits[%d] = {%s};" % (t, safename, len(bits_list), ", ".join(bits_list)))
centries_info.append('{"%s", %d, tile%d_%s_bits}' % (name, len(bits_list), t, safename))
print("static ConfigEntryPOD tile%d_config[%d] = {" % (t, len(centries_info)))
print(" " + ",\n ".join(centries_info))
print("};")
bba.l("tile%d_%s_bits" % (t, safename), "ConfigBitPOD")
for row, col in bits:
bba.u8(row, "row")
bba.u8(col, "col")
if len(bits) == 0:
bba.u8(0, "dummy")
centries_info.append((name, len(bits), t, safename))
for name, _, t, safename in centries_info:
if ("str_%s" % safename) not in bba.labels:
bba.l("str_%s" % safename, "char")
bba.s(name, None)
bba.l("tile%d_config" % t, "ConfigEntryPOD")
for _, num_bits, t, safename in centries_info:
bba.r("str_%s" % safename, "name")
bba.u32(num_bits, "num_bits")
bba.r("tile%d_%s_bits" % (t, safename), "num_bits")
if len(centries_info) == 0:
bba.u8(0, "dummy")
tileinfo.append("{%d, %d, %d, tile%d_config}" % (tile_sizes[t][0], tile_sizes[t][1], len(centries_info), t))
print("static uint8_t binblob_%s[] = {" % dev_name)
bba.write_c(sys.stdout)
print("};")
switchinfo = []
switchid = 0
for switch in switches: