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Some refactoring of Chip API (prep for chipdb refactoring)

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-16 15:23:04 +02:00
parent 5d343a168b
commit 6acf23cf37
7 changed files with 93 additions and 60 deletions
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17
common/log.h
View File

@ -56,13 +56,16 @@ NXP_NORETURN void logv_error(const char *format, va_list ap)
NXP_ATTRIBUTE(noreturn);
extern std::ostream clog;
void log(const char *format, ...);
void log_header(const char *format, ...);
void log_info(const char *format, ...);
void log_warning(const char *format, ...);
void log_warning_noprefix(const char *format, ...);
NXP_NORETURN void log_error(const char *format, ...);
NXP_NORETURN void log_cmd_error(const char *format, ...);
void log(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
void log_header(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
void log_info(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
void log_warning(const char *format, ...) NXP_ATTRIBUTE(format(printf, 1, 2));
void log_warning_noprefix(const char *format, ...)
NXP_ATTRIBUTE(format(printf, 1, 2));
NXP_NORETURN void log_error(const char *format, ...)
NXP_ATTRIBUTE(format(printf, 1, 2));
NXP_NORETURN void log_cmd_error(const char *format, ...)
NXP_ATTRIBUTE(format(printf, 1, 2));
void log_spacer();
void log_push();

40
common/route.cc
View File

@ -32,7 +32,7 @@ struct QueuedWire
WireId wire;
PipId pip;
float delay = 0, togo = 0;
delay_t delay = 0, togo = 0;
struct Greater
{
@ -63,10 +63,10 @@ struct Router
std::unordered_set<IdString> rippedNets;
int visitCnt = 0, revisitCnt = 0;
bool routedOkay = false;
float maxDelay = 0.0;
delay_t maxDelay = 0.0;
Router(Design *design, IdString net_name, bool verbose, bool ripup = false,
float ripup_pip_penalty = 5.0, float ripup_wire_penalty = 5.0)
delay_t ripup_pip_penalty = 5.0, delay_t ripup_wire_penalty = 5.0)
{
auto &chip = design->chip;
auto net_info = design->nets.at(net_name);
@ -148,7 +148,7 @@ struct Router
log(" Destination wire: %s\n",
chip.getWireName(dst_wire).c_str());
log(" Path delay estimate: %.2f\n",
chip.estimateDelay(src_wire, dst_wire));
float(chip.estimateDelay(src_wire, dst_wire)));
}
std::unordered_map<WireId, QueuedWire> visited;
@ -172,7 +172,7 @@ struct Router
queue.pop();
for (auto pip : chip.getPipsDownhill(qw.wire)) {
float next_delay = qw.delay;
delay_t next_delay = qw.delay;
visitCnt++;
if (!chip.checkPipAvail(pip)) {
@ -192,7 +192,8 @@ struct Router
log("Found better route to %s. Old vs new delay "
"estimate: %.2f %.2f\n",
chip.getWireName(next_wire).c_str(),
visited.at(next_wire).delay, next_delay);
float(visited.at(next_wire).delay),
float(next_delay));
#endif
revisitCnt++;
}
@ -228,7 +229,8 @@ struct Router
}
if (verbose)
log(" Final path delay: %.2f\n", visited[dst_wire].delay);
log(" Final path delay: %.2f\n",
float(visited[dst_wire].delay));
maxDelay = fmaxf(maxDelay, visited[dst_wire].delay);
if (verbose)
@ -238,7 +240,7 @@ struct Router
while (1) {
if (verbose)
log(" %8.2f %s\n", visited[cursor].delay,
log(" %8.2f %s\n", float(visited[cursor].delay),
chip.getWireName(cursor).c_str());
if (src_wires.count(cursor))
@ -282,9 +284,9 @@ NEXTPNR_NAMESPACE_BEGIN
void route_design(Design *design, bool verbose)
{
auto &chip = design->chip;
float maxDelay = 0.0;
float ripup_pip_penalty = 5.0;
float ripup_wire_penalty = 5.0;
delay_t maxDelay = 0.0;
delay_t ripup_pip_penalty = 5.0;
delay_t ripup_wire_penalty = 5.0;
log_info("Routing..\n");
@ -311,7 +313,7 @@ void route_design(Design *design, bool verbose)
log_info("found %d unrouted nets. starting routing procedure.\n",
int(netsQueue.size()));
float estimatedTotalDelay = 0.0;
delay_t estimatedTotalDelay = 0.0;
int estimatedTotalDelayCnt = 0;
for (auto net_name : netsQueue) {
@ -358,7 +360,8 @@ void route_design(Design *design, bool verbose)
}
log_info("estimated total wire delay: %.2f (avg %.2f)\n",
estimatedTotalDelay, estimatedTotalDelay / estimatedTotalDelayCnt);
float(estimatedTotalDelay),
float(estimatedTotalDelay) / estimatedTotalDelayCnt);
while (!netsQueue.empty()) {
int visitCnt = 0, revisitCnt = 0, netCnt = 0;
@ -389,8 +392,8 @@ void route_design(Design *design, bool verbose)
if (netCnt % 100 != 0)
log_info(" processed %d nets. (%d routed, %d failed)\n", netCnt,
netCnt - int(ripupQueue.size()), int(ripupQueue.size()));
log_info("routing pass visited %d PIPs (%.2f%% revisits).\n", visitCnt,
(100.0 * revisitCnt) / visitCnt);
log_info(" routing pass visited %d PIPs (%.2f%% revisits).\n",
visitCnt, (100.0 * revisitCnt) / visitCnt);
if (!ripupQueue.empty()) {
log_info(" failed to route %d nets. re-routing in ripup mode.\n",
@ -427,10 +430,13 @@ void route_design(Design *design, bool verbose)
if (netCnt % 100 != 0)
log_info(" routed %d nets, ripped %d nets.\n", netCnt, ripCnt);
log_info(" routing pass visited %d PIPs (%.2f%% revisits).\n",
visitCnt, (100.0 * revisitCnt) / visitCnt);
log_info("ripped up %d previously routed nets. continue routing.\n",
if (!netsQueue.empty())
log_info(" ripped up %d previously routed nets. continue "
"routing.\n",
int(netsQueue.size()));
ripup_pip_penalty *= 1.5;
@ -438,7 +444,7 @@ void route_design(Design *design, bool verbose)
}
}
log_info("routing complete. longest path delay: %.2f\n", maxDelay);
log_info("routing complete. longest path delay: %.2f\n", float(maxDelay));
}
NEXTPNR_NAMESPACE_END

4
dummy/chip.cc
View File

@ -141,14 +141,14 @@ const std::vector<PipId> &Chip::getWireAliases(WireId wire) const
// ---------------------------------------------------------------
bool Chip::estimatePosition(BelId bel, float &x, float &y) const
bool Chip::estimatePosition(BelId bel, int &x, int &y) const
{
x = 0.0;
y = 0.0;
return false;
}
float Chip::estimateDelay(WireId src, WireId dst) const { return 0.0; }
delay_t Chip::estimateDelay(WireId src, WireId dst) const { return 0.0; }
// ---------------------------------------------------------------

14
dummy/chip.h
View File

@ -26,13 +26,15 @@
NEXTPNR_NAMESPACE_BEGIN
typedef float delay_t;
struct DelayInfo
{
float delay = 0;
delay_t delay = 0;
float raiseDelay() const { return delay; }
float fallDelay() const { return delay; }
float avgDelay() const { return delay; }
delay_t raiseDelay() const { return delay; }
delay_t fallDelay() const { return delay; }
delay_t avgDelay() const { return delay; }
DelayInfo operator+(const DelayInfo &other) const
{
@ -108,8 +110,8 @@ struct Chip
const std::vector<PipId> &getPipsUphill(WireId wire) const;
const std::vector<PipId> &getWireAliases(WireId wire) const;
bool estimatePosition(BelId bel, float &x, float &y) const;
float estimateDelay(WireId src, WireId dst) const;
bool estimatePosition(BelId bel, int &x, int &y) const;
delay_t estimateDelay(WireId src, WireId dst) const;
std::vector<GraphicElement> getFrameGraphics() const;
std::vector<GraphicElement> getBelGraphics(BelId bel) const;

12
ice40/chip.cc
View File

@ -275,7 +275,7 @@ BelId Chip::getPackagePinBel(const std::string &pin) const
// -----------------------------------------------------------------------
bool Chip::estimatePosition(BelId bel, float &x, float &y) const
bool Chip::estimatePosition(BelId bel, int &x, int &y) const
{
assert(bel != BelId());
x = chip_info.bel_data[bel.index].x;
@ -284,15 +284,15 @@ bool Chip::estimatePosition(BelId bel, float &x, float &y) const
return chip_info.bel_data[bel.index].type != TYPE_SB_GB;
}
float Chip::estimateDelay(WireId src, WireId dst) const
delay_t Chip::estimateDelay(WireId src, WireId dst) const
{
assert(src != WireId());
float x1 = chip_info.wire_data[src.index].x;
float y1 = chip_info.wire_data[src.index].y;
delay_t x1 = chip_info.wire_data[src.index].x;
delay_t y1 = chip_info.wire_data[src.index].y;
assert(dst != WireId());
float x2 = chip_info.wire_data[dst.index].x;
float y2 = chip_info.wire_data[dst.index].y;
delay_t x2 = chip_info.wire_data[dst.index].x;
delay_t y2 = chip_info.wire_data[dst.index].y;
return fabsf(x1 - x2) + fabsf(y1 - y2);
}

58
ice40/chip.h
View File

@ -26,13 +26,15 @@
NEXTPNR_NAMESPACE_BEGIN
typedef int delay_t;
struct DelayInfo
{
float delay = 0;
delay_t delay = 0;
float raiseDelay() const { return delay; }
float fallDelay() const { return delay; }
float avgDelay() const { return delay; }
delay_t raiseDelay() const { return delay; }
delay_t fallDelay() const { return delay; }
delay_t avgDelay() const { return delay; }
DelayInfo operator+(const DelayInfo &other) const
{
@ -44,7 +46,7 @@ struct DelayInfo
// -----------------------------------------------------------------------
enum BelType
enum BelType : int32_t
{
TYPE_NONE,
TYPE_ICESTORM_LC,
@ -56,7 +58,7 @@ enum BelType
IdString belTypeToId(BelType type);
BelType belTypeFromId(IdString id);
enum PortPin
enum PortPin : int32_t
{
PIN_NONE,
#define X(t) PIN_##t,
@ -70,6 +72,26 @@ PortPin portPinFromId(IdString id);
// -----------------------------------------------------------------------
#if 0
template <typename T>
struct RelPtr {
int offset;
// RelPtr(T *ptr) : offset(reinterpret_cast<const char*>(ptr) -
// reinterpret_cast<const char*>(this)) {}
T&operator*() {
return *reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
}
T*operator->() {
return reinterpret_cast<T*>(reinterpret_cast<char*>(this) + offset);
}
};
#else
template <typename T> using RelPtr = T *;
#endif
struct BelWirePOD
{
int32_t wire_index;
@ -78,10 +100,10 @@ struct BelWirePOD
struct BelInfoPOD
{
const char *name;
RelPtr<char> name;
BelType type;
int num_bel_wires;
BelWirePOD *bel_wires;
int32_t num_bel_wires;
RelPtr<BelWirePOD> bel_wires;
int8_t x, y, z;
};
@ -94,7 +116,7 @@ struct BelPortPOD
struct PipInfoPOD
{
int32_t src, dst;
float delay;
int32_t delay;
int8_t x, y;
int16_t switch_mask;
int32_t switch_index;
@ -102,15 +124,15 @@ struct PipInfoPOD
struct WireInfoPOD
{
const char *name;
int num_uphill, num_downhill;
int *pips_uphill, *pips_downhill;
RelPtr<char> name;
int32_t num_uphill, num_downhill;
RelPtr<int32_t> pips_uphill, pips_downhill;
int num_bels_downhill;
int32_t num_bels_downhill;
BelPortPOD bel_uphill;
BelPortPOD *bels_downhill;
RelPtr<BelPortPOD> bels_downhill;
float x, y;
int8_t x, y;
};
struct PackagePinPOD
@ -694,8 +716,8 @@ struct Chip
// -------------------------------------------------
bool estimatePosition(BelId bel, float &x, float &y) const;
float estimateDelay(WireId src, WireId dst) const;
bool estimatePosition(BelId bel, int &x, int &y) const;
delay_t estimateDelay(WireId src, WireId dst) const;
// -------------------------------------------------

2
ice40/chipdb.py
View File

@ -430,7 +430,7 @@ for wire in range(num_wires):
avg_x /= len(wire_xy[wire])
avg_y /= len(wire_xy[wire])
info += "%f, %f}" % (avg_x, avg_y)
info += "%d, %d}" % (round(avg_x), round(avg_y))
wireinfo.append(info)