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machxo2: Misc tidying up

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-02-12 10:43:15 +00:00
parent 33eca9a3d2
commit 6de733b38c
2 changed files with 4 additions and 8 deletions
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5
machxo2/arch.cc
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@ -401,7 +401,10 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
{ {
ArcBounds bb; ArcBounds bb;
bb.x0 = std::min(src.location.x, dst.location.x);
bb.y0 = std::min(src.location.y, dst.location.y);
bb.x1 = std::max(src.location.x, dst.location.x);
bb.y1 = std::max(src.location.y, dst.location.y);
return bb; return bb;
} }

7
machxo2/archdefs.h
View File

@ -129,13 +129,6 @@ struct NetInfo;
struct ArchCellInfo struct ArchCellInfo
{ {
// Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
// value may share a tile (-1 = don't care, default if not set)
int user_group;
// Is a slice type primitive
bool is_slice;
// Only packing rule for slice type primitives is a single clock per tile
const NetInfo *slice_clk;
}; };
NEXTPNR_NAMESPACE_END NEXTPNR_NAMESPACE_END