machxo2: Misc tidying up
Signed-off-by: gatecat <gatecat@ds0.me>
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@ -401,7 +401,10 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
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{
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ArcBounds bb;
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bb.x0 = std::min(src.location.x, dst.location.x);
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bb.y0 = std::min(src.location.y, dst.location.y);
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bb.x1 = std::max(src.location.x, dst.location.x);
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bb.y1 = std::max(src.location.y, dst.location.y);
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return bb;
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}
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@ -129,13 +129,6 @@ struct NetInfo;
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struct ArchCellInfo
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{
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// Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
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// value may share a tile (-1 = don't care, default if not set)
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int user_group;
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// Is a slice type primitive
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bool is_slice;
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// Only packing rule for slice type primitives is a single clock per tile
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const NetInfo *slice_clk;
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};
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NEXTPNR_NAMESPACE_END
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