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Initial compiling version.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-01-26 14:45:54 -08:00
parent 561b519716
commit 6e68e8f097
2 changed files with 25 additions and 16 deletions
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9
fpga_interchange/arch.cc
View File

@ -349,6 +349,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getBelAttrs(BelId bel) const
delay_t Arch::estimateDelay(WireId src, WireId dst, bool debug) const
{
// FIXME: Implement when adding timing-driven place and route.
return 0;
}
@ -383,6 +384,7 @@ ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
delay_t Arch::getBoundingBoxCost(WireId src, WireId dst, int distance) const
{
// FIXME: Implement when adding timing-driven place and route.
return 0;
}
@ -393,6 +395,7 @@ delay_t Arch::getWireRipupDelayPenalty(WireId wire) const
delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
{
// FIXME: Implement when adding timing-driven place and route.
return 0;
}
@ -402,16 +405,19 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
bool Arch::pack()
{
// FIXME: Implement this
return false;
}
bool Arch::place()
{
// FIXME: Implement this
return false;
}
bool Arch::route()
{
// FIXME: Implement this
return false;
}
@ -442,16 +448,19 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
{
// FIXME: Implement when adding timing-driven place and route.
return false;
}
TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
{
// FIXME: Implement when adding timing-driven place and route.
return TMG_IGNORE;
}
TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
{
// FIXME: Implement when adding timing-driven place and route.
TimingClockingInfo info;
return info;
}

32
fpga_interchange/arch.h
View File

@ -53,16 +53,6 @@ template <typename T> struct RelPtr
};
NPNR_PACKED_STRUCT(struct SiteTypeInfoPOD {
// Name of this site type.
RelPtr<char> name;
// Lookup for site pip name to site pip index.
int32_t number_site_pips;
RelPtr<RelPtr<char>> site_pip_names;
});
// Flattened site indexing.
//
// To enable flat BelId.z spaces, every tile and sites within that tile are
@ -102,11 +92,15 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
});
NPNR_PACKED_STRUCT(struct TileWireInfoPOD {
int32_t name;
int32_t num_uphill, num_downhill;
int32_t name; // wire name constid
// Pip index inside tile
RelPtr<int32_t> pips_uphill, pips_downhill;
int32_t num_uphill;
RelPtr<int32_t> pips_uphill;
// Pip index inside tile
int32_t num_downhill;
RelPtr<int32_t> pips_downhill;
// Bel index inside tile
int32_t num_bel_pins;
@ -155,6 +149,7 @@ NPNR_PACKED_STRUCT(struct TileInstInfoPOD {
int32_t type;
// This array is root.tile_types[type].number_sites long.
// Index into root.sites
RelPtr<int32_t> sites;
// Number of tile wires; excluding any site-internal wires
@ -181,11 +176,17 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
int32_t version;
int32_t width, height;
int32_t num_tiles, num_tile_types;
int32_t num_sites, num_nodes;
int32_t num_tile_types;
RelPtr<TileTypeInfoPOD> tile_types;
int32_t num_sites;
RelPtr<SiteInstInfoPOD> sites;
int32_t num_tiles;
RelPtr<TileInstInfoPOD> tiles;
int32_t num_nodes;
RelPtr<NodeInfoPOD> nodes;
});
@ -1011,7 +1012,6 @@ struct Arch : BaseCtx
std::vector<GroupId> getGroupGroups(GroupId group) const { return {}; }
// -------------------------------------------------
mutable IdString gnd_glbl, gnd_row, vcc_glbl, vcc_row;
delay_t estimateDelay(WireId src, WireId dst, bool debug = false) const;
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;