Enable wires and add dummy wire type for now

gui/designwidget.cc

@@ -318,6 +318,11 @@ void DesignWidget::newContext(Context *ctx)
                 wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
             }
 #endif
+#ifdef ARCH_MACHXO2
+            for (const auto &wire : ctx->getWires()) {
+                wireMap[std::pair<int, int>(wire.location.x, wire.location.y)].push_back(wire);
+            }
+#endif
 #ifdef ARCH_GOWIN
             for (const auto &wire : ctx->getWires()) {
                 WireInfo wi = ctx->wire_info(wire);

machxo2/CMakeLists.txt

@@ -62,6 +62,7 @@ else()
                 -L ${TRELLIS_DATADIR}/util/common
                 -L ${TRELLIS_DATADIR}/timing/util
                 -p ${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+                -g ${CMAKE_CURRENT_SOURCE_DIR}/gfx.h
                 ${device}
                 > ${device_bba}.new
             # atomically update
@@ -69,6 +70,7 @@ else()
             DEPENDS
                 ${CMAKE_CURRENT_SOURCE_DIR}/facade_import.py
                 ${CMAKE_CURRENT_SOURCE_DIR}/constids.inc
+                ${CMAKE_CURRENT_SOURCE_DIR}/gfx.h
                 ${PREVIOUS_CHIPDB_TARGET}
             VERBATIM)
         list(APPEND all_device_bbas ${device_bba})

machxo2/arch.h

@@ -74,7 +74,8 @@ NPNR_PACKED_STRUCT(struct PipInfoPOD {
 
 NPNR_PACKED_STRUCT(struct WireInfoPOD {
     RelPtr<char> name;
-    int32_t tile_wire;
+    int16_t type;
+    int16_t tile_wire;
     int32_t num_uphill;
     int32_t num_downhill;
     RelPtr<PipLocatorPOD> pips_uphill;

machxo2/constids.inc

@@ -123,6 +123,9 @@ X(IO_TYPE)
 X(LOC)
 X(NOM_FREQ)
 X(VCC)
+
+X(WIRE_TYPE_NONE)
+
 X(machxo2)
 X(pack)
 X(place)

machxo2/facade_import.py

@@ -5,6 +5,8 @@ import sys
 from os import path
 
 tiletype_names = dict()
+gfx_wire_ids = dict()
+gfx_wire_names = list()
 
 parser = argparse.ArgumentParser(description="import MachXO2 routing and bels from Project Trellis")
 parser.add_argument("device", type=str, help="target device")
@@ -17,6 +19,24 @@ sys.path += args.libdir
 import pytrellis
 import database
 
+with open(args.gfxh) as f:
+    state = 0
+    for line in f:
+        if state == 0 and line.startswith("enum GfxTileWireId"):
+            state = 1
+        elif state == 1 and line.startswith("};"):
+            state = 0
+        elif state == 1 and (line.startswith("{") or line.strip() == ""):
+            pass
+        elif state == 1:
+            idx = len(gfx_wire_ids)
+            name = line.strip().rstrip(",")
+            gfx_wire_ids[name] = idx
+            gfx_wire_names.append(name)
+
+def wire_type(name):
+    return "WIRE_TYPE_NONE"
+
 # Get the index for a tiletype
 def get_tiletype_index(name):
     if name in tiletype_names:
@@ -283,12 +303,11 @@ def write_database(dev_name, chip, rg, endianness):
             for wire_idx in range(len(t.wires)):
                 wire = t.wires[wire_idx]
                 bba.s(rg.to_str(wire.name), "name")
-                # TODO: Padding until GUI support is added.
+                bba.u16(constids[wire_type(rg.to_str(wire.name))], "type")
-                # bba.u32(constids[wire_type(ddrg.to_str(wire.name))], "type")
+                if ("TILE_WIRE_" + rg.to_str(wire.name)) in gfx_wire_ids:
-                # if ("TILE_WIRE_" + ddrg.to_str(wire.name)) in gfx_wire_ids:
+                    bba.u16(gfx_wire_ids["TILE_WIRE_" + rg.to_str(wire.name)], "tile_wire")
-                #     bba.u32(gfx_wire_ids["TILE_WIRE_" + ddrg.to_str(wire.name)], "tile_wire")
+                else:
-                # else:
+                    bba.u16(0, "tile_wire")
-                bba.u32(0, "tile_wire")
                 bba.u32(len(wire.arcsUphill), "num_uphill")
                 bba.u32(len(wire.arcsDownhill), "num_downhill")
                 bba.r("loc%d_%d_wire%d_uppips" % (l.y, l.x, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")