ecp5: Adding complete binary blob writer to Trellis importer
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah
parent
ee45f57909
commit
6f90c3df61
2
ecp5/.gitignore
vendored
2
ecp5/.gitignore
vendored
@ -1,2 +1,2 @@
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__pycache__
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chipdbs/
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@ -1,11 +1,21 @@
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#!/usr/bin/env python3
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import pytrellis
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import database
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import argparse
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location_types = dict()
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type_at_location = dict()
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tiletype_names = dict()
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parser = argparse.ArgumentParser(description="import ECP5 routing and bels from Project Trellis")
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group = parser.add_mutually_exclusive_group()
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group.add_argument("-b", "--binary", action="store_true")
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group.add_argument("-c", "--c_file", action="store_true")
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parser.add_argument("device", type=str, help="target device")
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parser.add_argument("outfile", type=argparse.FileType('w'), help="output filename")
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parser.add_argument("-p", "--portspins", type=str, help="path to portpins.inc")
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args = parser.parse_args()
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def is_global(loc):
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return loc.x == -2 and loc.y == -2
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@ -20,6 +30,8 @@ def get_tiletype_index(name):
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return idx
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portpins = dict()
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loc_wire_indices = dict()
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loc_wires = dict()
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@ -65,19 +77,21 @@ def index_location_arcs(rg, x, y):
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loc_arcs[x, y] = list()
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rtile = rg.tiles[pytrellis.Location(x, y)]
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for arc in rtile.arcs:
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idx = len(loc_arcs)
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idx = len(loc_arcs[x, y])
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trid = arc.key()
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loc_arcs[x, y].append(trid)
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loc_arc_indices[x, y][trid] = idx
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def add_bel_input(bel_x, bel_y, bel_idx, bel_pin, wire_x, wire_y, wire_name):
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bel_pin = portpins[bel_pin]
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loc_bels[bel_x, bel_y][bel_idx][2].append((bel_pin, (wire_x, wire_y, loc_wire_indices[wire_x, wire_y][wire_name])))
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wire_bel_pins_downhill[wire_x, wire_y][loc_wire_indices[wire_x, wire_y][wire_name]].append((
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(bel_x, bel_y, bel_idx), bel_pin))
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def add_bel_output(bel_x, bel_y, bel_idx, bel_pin, wire_x, wire_y, wire_name):
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bel_pin = portpins[bel_pin]
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loc_bels[bel_x, bel_y][bel_idx][2].append((bel_pin, (wire_x, wire_y, loc_wire_indices[wire_x, wire_y][wire_name])))
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wire_bel_pins_uphill[wire_x, wire_y][loc_wire_indices[wire_x, wire_y][wire_name]].append((
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(bel_x, bel_y, bel_idx), bel_pin))
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@ -359,7 +373,7 @@ class BinaryBlobAssembler:
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print(file=f)
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if cursor in self.exports:
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print("#define %s ((%s*)(%s+%d))" % (
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self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
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self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
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else:
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print(" // [%d] %s" % (cursor, self.labels_byaddr[cursor]), file=f)
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bytecnt = 0
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@ -402,7 +416,7 @@ class BinaryBlobAssembler:
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print(file=f)
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for cursor in self.exports:
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print("#define %s ((%s*)(%s+%d))" % (
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self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
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self.labels_byaddr[cursor], self.ltypes_byaddr[cursor], self.cname, cursor), file=f)
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print("};", file=f)
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def write_uint64_c(self, f, ctype="const uint64_t"):
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@ -477,43 +491,139 @@ class BinaryBlobAssembler:
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f.buffer.write(self.data)
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def write_database(bba):
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bel_types = {
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"NONE": 0,
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"SLICE": 1,
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"PIO": 2
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}
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def write_database(dev_name, endianness):
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def write_loc(x, y, sym_name):
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bba.s16(x, "%s_x" % sym_name)
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bba.s16(y, "%s_y" % sym_name)
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bba.s16(x, "%s.x" % sym_name)
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bba.s16(y, "%s.y" % sym_name)
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bba = BinaryBlobAssembler("chipdb_blob_%s" % dev_name, endianness)
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bba.r("chip_info", "chip_info")
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for loctype, idx in sorted(location_types.items(), key=lambda x: x[1]):
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wires, arcs, bels = loctype
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bba.l("loc%d_pips" % idx, "PipInfoPOD")
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for arc in arcs:
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src_wire, dst_wire, configurable, tile_type = arc
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write_loc(src_wire[0], src_wire[1], "src")
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write_loc(dst_wire[0], dst_wire[1], "dst")
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bba.u32(src_wire[2], "src_idx")
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bba.u32(dst_wire[2], "dst_idx")
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bba.u32(1, "delay") # TODO:delay
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bba.u16(tile_type, "tile_type")
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bba.u8(1 if not configurable else 0, "pip_type")
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bba.u8(0, "padding")
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for wire_idx in range(len(wires)):
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wire = wires[wire_idx]
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name, downpips, uppips, downbels, upbels = wire
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if len(downpips) > 0:
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bba.l("loc%d_wire%d_downpips" % (idx, wire_idx), "PipLocatorPOD")
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for dp in downpips:
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write_loc(dp[0], dp[1], "rel_loc")
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bba.u32(dp[2], "idx")
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if len(uppips) > 0:
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bba.l("loc%d_wire%d_uppips" % (idx, wire_idx), "PipLocatorPOD")
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for up in uppips:
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write_loc(up[0], up[1], "rel_loc")
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bba.u32(up[2], "idx")
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if len(arcs) > 0:
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bba.l("loc%d_pips" % idx, "PipInfoPOD")
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for arc in arcs:
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src_wire, dst_wire, configurable, tile_type = arc
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write_loc(src_wire[0], src_wire[1], "src")
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write_loc(dst_wire[0], dst_wire[1], "dst")
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bba.u32(src_wire[2], "src_idx")
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bba.u32(dst_wire[2], "dst_idx")
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bba.u32(1, "delay") # TODO:delay
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bba.u16(tile_type, "tile_type")
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bba.u8(1 if not configurable else 0, "pip_type")
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bba.u8(0, "padding")
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if len(wires) > 0:
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for wire_idx in range(len(wires)):
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wire = wires[wire_idx]
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name, downpips, uppips, downbels, upbels = wire
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if len(downpips) > 0:
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bba.l("loc%d_wire%d_downpips" % (idx, wire_idx), "PipLocatorPOD")
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for dp in downpips:
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write_loc(dp[0], dp[1], "rel_loc")
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bba.u32(dp[2], "index")
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if len(uppips) > 0:
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bba.l("loc%d_wire%d_uppips" % (idx, wire_idx), "PipLocatorPOD")
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for up in uppips:
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write_loc(up[0], up[1], "rel_loc")
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bba.u32(up[2], "index")
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if len(downbels) > 0:
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bba.l("loc%d_wire%d_downbels" % (idx, wire_idx), "BelPortPOD")
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for db in downbels:
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bel, pin = db
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write_loc(bel[0], bel[1], "rel_bel_loc")
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bba.u32(bel[2], "bel_index")
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bba.u32(pin, "port")
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bba.l("loc%d_wires" % idx, "WireInfoPOD")
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for wire_idx in range(len(wires)):
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wire = wires[wire_idx]
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name, downpips, uppips, downbels, upbels = wire
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bba.s(name, "name")
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bba.u32(len(uppips), "num_uphill")
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bba.u32(len(downpips), "num_downhill")
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bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(uppips) > 0 else None, "pips_uphill")
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bba.r("loc%d_wire%d_downpips" % (idx, wire_idx) if len(downpips) > 0 else None, "pips_downhill")
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bba.u32(len(downbels), "num_bels_downhill")
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if len(upbels) == 1:
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bel, pin = upbels[0]
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write_loc(bel[0], bel[1], "uphill_bel_loc")
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bba.u32(bel[2], "uphill_bel_idx")
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bba.u32(pin, "uphill_bel_pin")
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else:
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write_loc(-1, -1, "bel_uphill.rel_bel_loc")
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bba.u32(0xFFFFFFFF, "bel_uphill.bel_index")
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bba.u32(0, "bel_uphill.port")
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bba.r("loc%d_wire%d_downbels" % (idx, wire_idx) if len(downbels) > 0 else None, "bels_downhill")
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if len(bels) > 0:
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for bel_idx in range(len(bels)):
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bel, beltype, pins = bels[bel_idx]
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bba.l("loc%d_bel%d_wires" % (idx, bel_idx), "BelPortPOD")
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for pin in pins:
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port, wire = pin
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write_loc(wire[0], wire[1], "rel_wire_loc")
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bba.u32(wire[2], "wire_index")
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bba.u32(port, "port")
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bba.l("loc%d_bels" % idx, "BelInfoPOD")
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for bel_idx in range(len(bels)):
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bel, beltype, pins = bels[bel_idx]
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bba.s(bel, "name")
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bba.u32(bel_types[beltype], "type")
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bba.u32(len(pins), "num_bel_wires")
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bba.r("loc%d_bel%d_wires" % (idx, bel_idx), "bel_wires")
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bba.l("locations", "LocationTypePOD")
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for loctype, idx in sorted(location_types.items(), key=lambda x: x[1]):
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wires, arcs, bels = loctype
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bba.u32(len(bels), "num_bels")
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bba.u32(len(wires), "num_wires")
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bba.u32(len(arcs), "num_pips")
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bba.r("loc%d_bels" % idx if len(bels) > 0 else None, "bel_data")
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bba.r("loc%d_wires" % idx if len(wires) > 0 else None, "wire_data")
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bba.r("loc%d_pips" % idx if len(arcs) > 0 else None, "pips_data")
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bba.l("location_types", "int32_t")
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for y in range(0, max_row+1):
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for x in range(0, max_col+1):
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bba.u32(type_at_location[x, y], "loctype")
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bba.l("chip_info")
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bba.u32(max_col + 1, "width")
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bba.u32(max_row + 1, "height")
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bba.u32((max_col + 1) * (max_row + 1), "num_tiles")
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bba.u32(len(location_types), "num_location_types")
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bba.r("locations", "locations")
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bba.r("location_types", "location_type")
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bba.finalize()
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return bba
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dev_names = {"LFE5U-25F": "25k", "LFE5U-45F": "45k", "LFE5U-85F": "85k"}
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def main():
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global max_row, max_col
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pytrellis.load_database(database.get_db_root())
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args = parser.parse_args()
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# Read port pin file
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with open(args.portspins) as f:
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for line in f:
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line = line.replace("(", " ")
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line = line.replace(")", " ")
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line = line.split()
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if len(line) == 0:
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continue
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assert len(line) == 2
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assert line[0] == "X"
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idx = len(portpins) + 1
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portpins[line[1]] = idx
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print("Initialising chip...")
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chip = pytrellis.Chip("LFE5U-25F")
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chip = pytrellis.Chip(args.device)
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print("Building routing graph...")
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rg = chip.get_routing_graph()
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max_row = chip.get_max_row()
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@ -535,7 +645,23 @@ def main():
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for x in range(0, max_col + 1):
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print(" At R{}C{}".format(y, x))
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import_location(rg, x, y)
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print("{} unique location types".format(len(location_types)))
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bba = write_database(dev_names[args.device], "le")
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if args.c_file:
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print('#include "nextpnr.h"', file=args.outfile)
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print('NEXTPNR_NAMESPACE_BEGIN', file=args.outfile)
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if args.binary:
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bba.write_binary(args.outfile)
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if args.c_file:
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bba.write_string_c(args.outfile)
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if args.c_file:
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print('NEXTPNR_NAMESPACE_END', file=args.outfile)
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if __name__ == "__main__":
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main()
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