caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Deterministic chipdb blobs

Browse Source 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-07-11 18:36:15 +02:00
parent 297a013e4d
commit 6ffae27aa1
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ecp5/trellis_import.py
View File

@ -331,7 +331,7 @@ class BinaryBlobAssembler:
def finalize(self): def finalize(self):
assert not self.finalized assert not self.finalized
for s, index in self.strings.items(): for s, index in sorted(self.strings.items()):
self.l("str%d" % index, "char") self.l("str%d" % index, "char")
for c in s: for c in s:
self.data.append(ord(c)) self.data.append(ord(c))

4
ice40/chipdb.py
View File

@ -712,7 +712,7 @@ class BinaryBlobAssembler:
def finalize(self): def finalize(self):
assert not self.finalized assert not self.finalized
for s, index in self.strings.items(): for s, index in sorted(self.strings.items()):
self.l("str%d" % index, "char") self.l("str%d" % index, "char")
for c in s: for c in s:
self.data.append(ord(c)) self.data.append(ord(c))
@ -947,7 +947,7 @@ for wire in range(num_wires):
if wire in wire_downhill_belports: if wire in wire_downhill_belports:
num_bels_downhill = len(wire_downhill_belports[wire]) num_bels_downhill = len(wire_downhill_belports[wire])
bba.l("wire%d_downbels" % wire, "BelPortPOD") bba.l("wire%d_downbels" % wire, "BelPortPOD")
for belport in wire_downhill_belports[wire]: for belport in sorted(wire_downhill_belports[wire]):
bba.u32(belport[0], "bel_index") bba.u32(belport[0], "bel_index")
bba.u32(portpins[belport[1]], "port") bba.u32(portpins[belport[1]], "port")
else: else: