cyclonev: basic platform
This commit is contained in:
Dan Ravensloft
gatecat
parent
1b5767928d
commit
6ffbb9ed87
@ -97,7 +97,7 @@ set(PROGRAM_PREFIX "" CACHE STRING "Name prefix for executables")
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# List of families to build
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# List of families to build
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set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange machxo2)
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set(FAMILIES generic ice40 ecp5 nexus gowin fpga_interchange machxo2)
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set(STABLE_FAMILIES generic ice40 ecp5)
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set(STABLE_FAMILIES generic ice40 ecp5)
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set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange machxo2)
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set(EXPERIMENTAL_FAMILIES nexus gowin fpga_interchange machxo2 cyclonev)
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set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
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set(ARCH "" CACHE STRING "Architecture family for nextpnr build")
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set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
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set_property(CACHE ARCH PROPERTY STRINGS ${FAMILIES})
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18
cyclonev/arch.cc
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18
cyclonev/arch.cc
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@ -0,0 +1,18 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2020 Lofty <dan.ravensloft@gmail.com
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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373
cyclonev/arch.h
Normal file
373
cyclonev/arch.h
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@ -0,0 +1,373 @@
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/*
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* nextpnr -- Next Generation Place and Route
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*
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* Copyright (C) 2020 Lofty <dan.ravensloft@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef NEXTPNR_H
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#error Include "arch.h" via "nextpnr.h" only.
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#endif
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NEXTPNR_NAMESPACE_BEGIN
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struct BelIterator
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{
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int cursor;
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BelIterator operator++()
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{
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cursor++;
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return *this;
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}
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BelIterator operator++(int)
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{
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BelIterator prior(*this);
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cursor++;
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return prior;
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}
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bool operator!=(const BelIterator &other) const { return cursor != other.cursor; }
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bool operator==(const BelIterator &other) const { return cursor == other.cursor; }
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BelId operator*() const
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{
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BelId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct BelRange
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{
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BelIterator b, e;
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BelIterator begin() const { return b; }
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BelIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct BelPinIterator
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{
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const /* something */ int *ptr = nullptr;
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void operator++() { ptr++; }
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bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; }
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BelPin operator*() const
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{
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BelPin ret;
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return ret;
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}
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};
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struct BelPinRange
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{
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BelPinIterator b, e;
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BelPinIterator begin() const { return b; }
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BelPinIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct WireIterator
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{
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int cursor = -1;
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void operator++() { cursor++; }
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bool operator!=(const WireIterator &other) const { return cursor != other.cursor; }
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WireId operator*() const
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{
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WireId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct WireRange
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{
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WireIterator b, e;
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WireIterator begin() const { return b; }
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WireIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct AllPipIterator
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{
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int cursor = -1;
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void operator++() { cursor++; }
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bool operator!=(const AllPipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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ret.index = cursor;
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return ret;
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}
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};
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struct AllPipRange
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{
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AllPipIterator b, e;
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AllPipIterator begin() const { return b; }
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AllPipIterator end() const { return e; }
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};
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// -----------------------------------------------------------------------
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struct PipIterator
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{
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const int *cursor = nullptr;
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void operator++() { cursor++; }
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bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
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PipId operator*() const
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{
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PipId ret;
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ret.index = *cursor;
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return ret;
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}
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};
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struct PipRange
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{
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PipIterator b, e;
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PipIterator begin() const { return b; }
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PipIterator end() const { return e; }
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};
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struct ArchArgs
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{
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};
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struct Arch : BaseCtx
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{
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ArchArgs args;
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Arch(ArchArgs args);
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std::string getChipName() const;
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IdString archId() const { return id("cyclonev"); }
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ArchArgs archArgs() const;
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IdString archArgsToId(ArchArgs args) const;
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// -------------------------------------------------
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int getGridDimX() const;
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int getGridDimY() const;
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int getTileBelDimZ(int, int) const;
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int getTilePipDimZ(int, int) const;
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// -------------------------------------------------
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BelId getBelByName(IdString name) const;
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IdString getBelName(BelId bel) const;
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uint32_t getBelChecksum(BelId bel) const;
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength);
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void unbindBel(BelId bel);
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bool checkBelAvail(BelId bel) const;
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CellInfo *getBoundBelCell(BelId bel) const;
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CellInfo *getConflictingBelCell(BelId bel) const;
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BelRange getBels() const;
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Loc getBelLocation(BelId bel) const;
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BelId getBelByLocation(Loc loc) const;
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BelRange getBelsByTile(int x, int y) const;
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bool getBelGlobalBuf(BelId bel) const;
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IdString getBelType(BelId bel) const;
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std::vector<std::pair<IdString, std::string>> getBelAttrs(BelId bel) const;
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WireId getBelPinWire(BelId bel, IdString pin) const;
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PortType getBelPinType(BelId bel, IdString pin) const;
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std::vector<IdString> getBelPins(BelId bel) const;
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bool isBelLocked(BelId bel) const;
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// -------------------------------------------------
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WireId getWireByName(IdString name) const;
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IdString getWireName(WireId wire) const;
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IdString getWireType(WireId wire) const;
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std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId wire) const;
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uint32_t getWireChecksum(WireId wire) const;
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength);
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void unbindWire(WireId wire);
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bool checkWireAvail(WireId wire) const;
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NetInfo *getBoundWireNet(WireId wire) const;
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WireId getConflictingWireWire(WireId wire) const;
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NetInfo *getConflictingWireNet(WireId wire) const;
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DelayInfo getWireDelay(WireId wire) const;
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BelPinRange getWireBelPins(WireId wire) const;
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WireRange getWires() const;
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// -------------------------------------------------
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PipId getPipByName(IdString name) const;
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength);
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void unbindPip(PipId pip);
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bool checkPipAvail(PipId pip) const;
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NetInfo *getBoundPipNet(PipId pip) const;
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WireId getConflictingPipWire(PipId pip) const;
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NetInfo *getConflictingPipNet(PipId pip) const;
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AllPipRange getPips() const;
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Loc getPipLocation(PipId pip) const;
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IdString getPipName(PipId pip) const;
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IdString getPipType(PipId pip) const;
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std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId pip) const;
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uint32_t getPipChecksum(PipId pip) const;
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WireId getPipSrcWire(PipId pip) const;
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WireId getPipDstWire(PipId pip) const;
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DelayInfo getPipDelay(PipId pip) const;
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PipRange getPipsDownhill(WireId wire) const;
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PipRange getPipsUphill(WireId wire) const;
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PipRange getWireAliases(WireId wire) const;
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BelId getPackagePinBel(const std::string &pin) const;
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std::string getBelPackagePin(BelId bel) const;
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// -------------------------------------------------
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GroupId getGroupByName(IdString name) const;
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IdString getGroupName(GroupId group) const;
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std::vector<GroupId> getGroups() const;
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std::vector<BelId> getGroupBels(GroupId group) const;
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std::vector<WireId> getGroupWires(GroupId group) const;
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std::vector<PipId> getGroupPips(GroupId group) const;
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std::vector<GroupId> getGroupGroups(GroupId group) const;
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// -------------------------------------------------
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const;
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delay_t getRipupDelayPenalty() const;
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float getDelayNS(delay_t v) const;
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DelayInfo getDelayFromNS(float ns) const;
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uint32_t getDelayChecksum(delay_t v) const;
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bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
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ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
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// -------------------------------------------------
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bool pack();
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bool place();
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bool route();
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// -------------------------------------------------
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std::vector<GraphicElement> getDecalGraphics(DecalId decal) const;
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DecalXY getBelDecal(BelId bel) const;
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DecalXY getWireDecal(WireId wire) const;
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DecalXY getPipDecal(PipId pip) const;
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DecalXY getGroupDecal(GroupId group) const;
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// -------------------------------------------------
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// Get the delay through a cell from one port to another, returning false
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// if no path exists. This only considers combinational delays, as required by the Arch API
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bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
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// getCellDelayInternal is similar to the above, but without false path checks and including clock to out delays
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// for internal arch use only
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bool getCellDelayInternal(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
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// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
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TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
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// Get the TimingClockingInfo of a port
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TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
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// Return true if a port is a net
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bool isGlobalNet(const NetInfo *net) const;
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// -------------------------------------------------
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// Perform placement validity checks, returning false on failure (all
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// implemented in arch_place.cc)
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// Whether or not a given cell can be placed at a given Bel
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// This is not intended for Bel type checks, but finer-grained constraints
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// such as conflicting set/reset signals, etc
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bool isValidBelForCell(CellInfo *cell, BelId bel) const;
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// Return true whether all Bels at a given location are valid
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bool isBelLocationValid(BelId bel) const;
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// Helper function for above
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bool logicCellsCompatible(const CellInfo **it, const size_t size) const;
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// -------------------------------------------------
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// Assign architecure-specific arguments to nets and cells, which must be
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// called between packing or further
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// netlist modifications, and validity checks
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void assignArchInfo();
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void assignCellInfo(CellInfo *cell);
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// -------------------------------------------------
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BelPin getIOBSharingPLLPin(BelId pll, IdString pll_pin) const;
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int getDrivenGlobalNetwork(BelId bel) const;
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static const std::string defaultPlacer;
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static const std::vector<std::string> availablePlacers;
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static const std::string defaultRouter;
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static const std::vector<std::string> availableRouters;
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};
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NEXTPNR_NAMESPACE_END
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187
cyclonev/archdefs.h
Normal file
187
cyclonev/archdefs.h
Normal file
@ -0,0 +1,187 @@
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/*
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||||||
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* nextpnr -- Next Generation Place and Route
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*
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||||||
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* Copyright (C) 2020 Lofty <dan.ravensloft@gmail.com>
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*
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||||||
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* Permission to use, copy, modify, and/or distribute this software for any
|
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||||
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||||
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||||
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
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*
|
||||||
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*/
|
||||||
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|
||||||
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#ifndef NEXTPNR_H
|
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|
#error Include "archdefs.h" via "nextpnr.h" only.
|
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|
#endif
|
||||||
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|
||||||
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NEXTPNR_NAMESPACE_BEGIN
|
||||||
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|
||||||
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typedef int delay_t;
|
||||||
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|
||||||
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struct DelayInfo
|
||||||
|
{
|
||||||
|
delay_t delay = 0;
|
||||||
|
|
||||||
|
delay_t minRaiseDelay() const { return delay; }
|
||||||
|
delay_t maxRaiseDelay() const { return delay; }
|
||||||
|
|
||||||
|
delay_t minFallDelay() const { return delay; }
|
||||||
|
delay_t maxFallDelay() const { return delay; }
|
||||||
|
|
||||||
|
delay_t minDelay() const { return delay; }
|
||||||
|
delay_t maxDelay() const { return delay; }
|
||||||
|
|
||||||
|
DelayInfo operator+(const DelayInfo &other) const
|
||||||
|
{
|
||||||
|
DelayInfo ret;
|
||||||
|
ret.delay = this->delay + other.delay;
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
struct BelId
|
||||||
|
{
|
||||||
|
int32_t index = -1;
|
||||||
|
|
||||||
|
bool operator==(const BelId &other) const { return index == other.index; }
|
||||||
|
bool operator!=(const BelId &other) const { return index != other.index; }
|
||||||
|
bool operator<(const BelId &other) const { return index < other.index; }
|
||||||
|
};
|
||||||
|
|
||||||
|
struct WireId
|
||||||
|
{
|
||||||
|
int32_t index = -1;
|
||||||
|
|
||||||
|
bool operator==(const WireId &other) const { return index == other.index; }
|
||||||
|
bool operator!=(const WireId &other) const { return index != other.index; }
|
||||||
|
bool operator<(const WireId &other) const { return index < other.index; }
|
||||||
|
};
|
||||||
|
|
||||||
|
struct PipId
|
||||||
|
{
|
||||||
|
int32_t index = -1;
|
||||||
|
|
||||||
|
bool operator==(const PipId &other) const { return index == other.index; }
|
||||||
|
bool operator!=(const PipId &other) const { return index != other.index; }
|
||||||
|
bool operator<(const PipId &other) const { return index < other.index; }
|
||||||
|
};
|
||||||
|
|
||||||
|
struct GroupId
|
||||||
|
{
|
||||||
|
enum : int8_t
|
||||||
|
{
|
||||||
|
TYPE_NONE
|
||||||
|
} type = TYPE_NONE;
|
||||||
|
int8_t x = 0, y = 0;
|
||||||
|
|
||||||
|
bool operator==(const GroupId &other) const { return (type == other.type) && (x == other.x) && (y == other.y); }
|
||||||
|
bool operator!=(const GroupId &other) const { return (type != other.type) || (x != other.x) || (y == other.y); }
|
||||||
|
};
|
||||||
|
|
||||||
|
struct DecalId
|
||||||
|
{
|
||||||
|
enum : int8_t
|
||||||
|
{
|
||||||
|
TYPE_NONE,
|
||||||
|
TYPE_BEL,
|
||||||
|
TYPE_WIRE,
|
||||||
|
TYPE_PIP,
|
||||||
|
TYPE_GROUP
|
||||||
|
} type = TYPE_NONE;
|
||||||
|
int32_t index = -1;
|
||||||
|
bool active = false;
|
||||||
|
|
||||||
|
bool operator==(const DecalId &other) const { return (type == other.type) && (index == other.index); }
|
||||||
|
bool operator!=(const DecalId &other) const { return (type != other.type) || (index != other.index); }
|
||||||
|
};
|
||||||
|
|
||||||
|
struct ArchNetInfo
|
||||||
|
{
|
||||||
|
bool is_global = false;
|
||||||
|
bool is_reset = false, is_enable = false;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct NetInfo;
|
||||||
|
|
||||||
|
struct ArchCellInfo
|
||||||
|
{
|
||||||
|
union
|
||||||
|
{
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
bool dffEnable;
|
||||||
|
bool carryEnable;
|
||||||
|
bool negClk;
|
||||||
|
int inputCount;
|
||||||
|
const NetInfo *clk, *cen, *sr;
|
||||||
|
} lcInfo;
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
bool lvds;
|
||||||
|
bool global;
|
||||||
|
bool negtrig;
|
||||||
|
int pintype;
|
||||||
|
// TODO: clk packing checks...
|
||||||
|
} ioInfo;
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
bool forPadIn;
|
||||||
|
} gbInfo;
|
||||||
|
struct
|
||||||
|
{
|
||||||
|
bool ledCurConnected;
|
||||||
|
} ledInfo;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
NEXTPNR_NAMESPACE_END
|
||||||
|
|
||||||
|
namespace std {
|
||||||
|
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelId>
|
||||||
|
{
|
||||||
|
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const noexcept { return hash<int>()(bel.index); }
|
||||||
|
};
|
||||||
|
|
||||||
|
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
|
||||||
|
{
|
||||||
|
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
|
||||||
|
{
|
||||||
|
return hash<int>()(wire.index);
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId>
|
||||||
|
{
|
||||||
|
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &pip) const noexcept { return hash<int>()(pip.index); }
|
||||||
|
};
|
||||||
|
|
||||||
|
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX GroupId>
|
||||||
|
{
|
||||||
|
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX GroupId &group) const noexcept
|
||||||
|
{
|
||||||
|
std::size_t seed = 0;
|
||||||
|
boost::hash_combine(seed, hash<int>()(group.type));
|
||||||
|
boost::hash_combine(seed, hash<int>()(group.x));
|
||||||
|
boost::hash_combine(seed, hash<int>()(group.y));
|
||||||
|
return seed;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX DecalId>
|
||||||
|
{
|
||||||
|
std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DecalId &decal) const noexcept
|
||||||
|
{
|
||||||
|
std::size_t seed = 0;
|
||||||
|
boost::hash_combine(seed, hash<int>()(decal.type));
|
||||||
|
boost::hash_combine(seed, hash<int>()(decal.index));
|
||||||
|
return seed;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
} // namespace std
|
||||||
0
cyclonev/family.cmake
Normal file
0
cyclonev/family.cmake
Normal file
Loading…
Reference in New Issue
Block a user