ice40: Make assignArchArgs a Arch method; call also after legaliser
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -697,4 +697,34 @@ bool Arch::isGlobalNet(const NetInfo *net) const
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return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out;
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}
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// Assign arch arg info
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void Arch::assignArchArgs()
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{
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for (auto &net : getCtx()->nets) {
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NetInfo *ni = net.second.get();
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if (isGlobalNet(ni))
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ni->is_global = true;
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}
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for (auto &cell : getCtx()->cells) {
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CellInfo *ci = cell.second.get();
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ci->belType = belTypeFromId(ci->type);
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if (ci->type == id_icestorm_lc) {
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ci->lcInfo.dffEnable = bool_or_default(ci->params, id_dff_en);
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ci->lcInfo.negClk = bool_or_default(ci->params, id_neg_clk);
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ci->lcInfo.clk = get_net_or_empty(ci, id_clk);
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ci->lcInfo.cen = get_net_or_empty(ci, id_cen);
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ci->lcInfo.sr = get_net_or_empty(ci, id_sr);
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ci->lcInfo.inputCount = 0;
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if (get_net_or_empty(ci, id_i0))
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ci->lcInfo.inputCount++;
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if (get_net_or_empty(ci, id_i1))
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ci->lcInfo.inputCount++;
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if (get_net_or_empty(ci, id_i2))
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ci->lcInfo.inputCount++;
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if (get_net_or_empty(ci, id_i3))
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ci->lcInfo.inputCount++;
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}
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}
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}
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NEXTPNR_NAMESPACE_END
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@ -705,6 +705,11 @@ struct Arch : BaseCtx
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// Helper function for above
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bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
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// -------------------------------------------------
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// Assign architecure-specific arguments to nets and cells, which must be called between packing or further
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// netlist modifications, and validity checks
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void assignArchArgs();
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IdString id_glb_buf_out;
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IdString id_icestorm_lc, id_sb_io, id_sb_gb;
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IdString id_cen, id_clk, id_sr;
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@ -575,36 +575,6 @@ static void pack_special(Context *ctx)
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}
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}
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// Assign arch arg info
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static void assign_archargs(Context *ctx)
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{
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for (auto &net : ctx->nets) {
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NetInfo *ni = net.second.get();
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if (ctx->isGlobalNet(ni))
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ni->is_global = true;
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}
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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ci->belType = ctx->belTypeFromId(ci->type);
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if (is_lc(ctx, ci)) {
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ci->lcInfo.dffEnable = bool_or_default(ci->params, ctx->id("DFF_ENABLE"));
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ci->lcInfo.negClk = bool_or_default(ci->params, ctx->id("NEG_CLK"));
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ci->lcInfo.clk = get_net_or_empty(ci, ctx->id("CLK"));
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ci->lcInfo.cen = get_net_or_empty(ci, ctx->id("CEN"));
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ci->lcInfo.sr = get_net_or_empty(ci, ctx->id("SR"));
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ci->lcInfo.inputCount = 0;
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if (get_net_or_empty(ci, ctx->id("I0")))
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ci->lcInfo.inputCount++;
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if (get_net_or_empty(ci, ctx->id("I1")))
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ci->lcInfo.inputCount++;
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if (get_net_or_empty(ci, ctx->id("I2")))
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ci->lcInfo.inputCount++;
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if (get_net_or_empty(ci, ctx->id("I3")))
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ci->lcInfo.inputCount++;
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}
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}
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}
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// Main pack function
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bool Arch::pack()
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{
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@ -619,7 +589,7 @@ bool Arch::pack()
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pack_carries(ctx);
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pack_ram(ctx);
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pack_special(ctx);
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assign_archargs(ctx);
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ctx->assignArchArgs();
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log_info("Checksum: 0x%08x\n", ctx->checksum());
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return true;
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} catch (log_execution_error_exception) {
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@ -127,6 +127,7 @@ class PlacementLegaliser
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legalise_others();
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legalise_logic_tiles();
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bool replaced_cells = replace_cells();
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ctx->assignArchArgs();
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return legalised_carries && replaced_cells;
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}
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