ice40: Make assignArchArgs a Arch method; call also after legaliser

Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-18 12:21:02 +02:00
parent c75a924c3f
commit 70cfa7a6a4
4 changed files with 37 additions and 31 deletions

View File

@ -697,4 +697,34 @@ bool Arch::isGlobalNet(const NetInfo *net) const
return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out;
}
// Assign arch arg info
void Arch::assignArchArgs()
{
for (auto &net : getCtx()->nets) {
NetInfo *ni = net.second.get();
if (isGlobalNet(ni))
ni->is_global = true;
}
for (auto &cell : getCtx()->cells) {
CellInfo *ci = cell.second.get();
ci->belType = belTypeFromId(ci->type);
if (ci->type == id_icestorm_lc) {
ci->lcInfo.dffEnable = bool_or_default(ci->params, id_dff_en);
ci->lcInfo.negClk = bool_or_default(ci->params, id_neg_clk);
ci->lcInfo.clk = get_net_or_empty(ci, id_clk);
ci->lcInfo.cen = get_net_or_empty(ci, id_cen);
ci->lcInfo.sr = get_net_or_empty(ci, id_sr);
ci->lcInfo.inputCount = 0;
if (get_net_or_empty(ci, id_i0))
ci->lcInfo.inputCount++;
if (get_net_or_empty(ci, id_i1))
ci->lcInfo.inputCount++;
if (get_net_or_empty(ci, id_i2))
ci->lcInfo.inputCount++;
if (get_net_or_empty(ci, id_i3))
ci->lcInfo.inputCount++;
}
}
}
NEXTPNR_NAMESPACE_END

View File

@ -705,6 +705,11 @@ struct Arch : BaseCtx
// Helper function for above
bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const;
// -------------------------------------------------
// Assign architecure-specific arguments to nets and cells, which must be called between packing or further
// netlist modifications, and validity checks
void assignArchArgs();
IdString id_glb_buf_out;
IdString id_icestorm_lc, id_sb_io, id_sb_gb;
IdString id_cen, id_clk, id_sr;

View File

@ -575,36 +575,6 @@ static void pack_special(Context *ctx)
}
}
// Assign arch arg info
static void assign_archargs(Context *ctx)
{
for (auto &net : ctx->nets) {
NetInfo *ni = net.second.get();
if (ctx->isGlobalNet(ni))
ni->is_global = true;
}
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
ci->belType = ctx->belTypeFromId(ci->type);
if (is_lc(ctx, ci)) {
ci->lcInfo.dffEnable = bool_or_default(ci->params, ctx->id("DFF_ENABLE"));
ci->lcInfo.negClk = bool_or_default(ci->params, ctx->id("NEG_CLK"));
ci->lcInfo.clk = get_net_or_empty(ci, ctx->id("CLK"));
ci->lcInfo.cen = get_net_or_empty(ci, ctx->id("CEN"));
ci->lcInfo.sr = get_net_or_empty(ci, ctx->id("SR"));
ci->lcInfo.inputCount = 0;
if (get_net_or_empty(ci, ctx->id("I0")))
ci->lcInfo.inputCount++;
if (get_net_or_empty(ci, ctx->id("I1")))
ci->lcInfo.inputCount++;
if (get_net_or_empty(ci, ctx->id("I2")))
ci->lcInfo.inputCount++;
if (get_net_or_empty(ci, ctx->id("I3")))
ci->lcInfo.inputCount++;
}
}
}
// Main pack function
bool Arch::pack()
{
@ -619,7 +589,7 @@ bool Arch::pack()
pack_carries(ctx);
pack_ram(ctx);
pack_special(ctx);
assign_archargs(ctx);
ctx->assignArchArgs();
log_info("Checksum: 0x%08x\n", ctx->checksum());
return true;
} catch (log_execution_error_exception) {

View File

@ -127,6 +127,7 @@ class PlacementLegaliser
legalise_others();
legalise_logic_tiles();
bool replaced_cells = replace_cells();
ctx->assignArchArgs();
return legalised_carries && replaced_cells;
}