diff --git a/common/place.cc b/common/place.cc index 8f174478..17b31c69 100644 --- a/common/place.cc +++ b/common/place.cc @@ -41,13 +41,13 @@ void place_design(Design *design) // Initial constraints placer for (auto cell_entry : design->cells) { CellInfo *cell = cell_entry.second; - auto loc = cell->attrs.find("LOC"); + auto loc = cell->attrs.find("BEL"); if (loc != cell->attrs.end()) { std::string loc_name = loc->second; BelId bel = design->chip.getBelByName(IdString(loc_name)); if (bel == BelId()) { log_error("No Bel named \'%s\' located for " - "this chip (processing LOC on \'%s\')\n", + "this chip (processing BEL attribute on \'%s\')\n", loc_name.c_str(), cell->name.c_str()); } @@ -112,7 +112,7 @@ void place_design(Design *design) design->chip.bindBel(cell->bel, cell->name); // Back annotate location - cell->attrs["LOC"] = design->chip.getBelName(cell->bel); + cell->attrs["BEL"] = design->chip.getBelName(cell->bel); } } } diff --git a/ice40/blinky.v b/ice40/blinky.v index 80f92b06..7fd3a0cf 100644 --- a/ice40/blinky.v +++ b/ice40/blinky.v @@ -7,8 +7,8 @@ module blinky ( output led5_pin ); wire clk, led1, led2, led3, led4, led5; - - (* LOC="0_3_lc0" *) + + (* BEL="13_12_io1" *) SB_IO #( .PIN_TYPE(6'b 0110_01), .PULLUP(1'b0), @@ -25,8 +25,8 @@ module blinky ( .D_IN_0(), .D_IN_1() ); - - (* LOC="0_3_lc1" *) + + (* BEL="13_12_io0" *) SB_IO #( .PIN_TYPE(6'b 0110_01), .PULLUP(1'b0), @@ -44,7 +44,7 @@ module blinky ( .D_IN_1() ); - (* LOC="5_17_lc1" *) + (* BEL="13_11_io1" *) SB_IO #( .PIN_TYPE(6'b 0110_01), .PULLUP(1'b0), @@ -62,7 +62,7 @@ module blinky ( .D_IN_1() ); - (* LOC="10_0_lc1" *) + (* BEL="13_11_io0" *) SB_IO #( .PIN_TYPE(6'b 0110_01), .PULLUP(1'b0), @@ -80,7 +80,7 @@ module blinky ( .D_IN_1() ); - (* LOC="12_17_lc0" *) + (* BEL="13_9_io1" *) SB_IO #( .PIN_TYPE(6'b 0110_01), .PULLUP(1'b0), @@ -98,7 +98,7 @@ module blinky ( .D_IN_1() ); - (* LOC="0_6_lc0" *) + (* BEL="0_8_io1" *) SB_IO #( .PIN_TYPE(6'b 0000_01), .PULLUP(1'b0), diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 78ba2e46..b4240e2d 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -186,7 +186,7 @@ def add_bel_lc(x, y, z): def add_bel_io(x, y, z): bel = len(bel_name) - bel_name.append("%d_%d_lc%d" % (x, y, z)) + bel_name.append("%d_%d_io%d" % (x, y, z)) bel_type.append("SB_IO") bel_pos.append((x, y, z)) bel_wires.append(list())