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Fixing 5k bitstream gen and place heuristics

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-22 12:34:42 +02:00
parent 2c98231f88
commit 71176ac538
2 changed files with 14 additions and 4 deletions
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5
common/place_sa.cc
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@ -410,9 +410,8 @@ class SAPlacer
delta = new_wirelength - curr_wirelength;
n_move++;
// SA acceptance criterea
if (delta < 0 || (temp > 1e-6 &&
(ctx->rng() / float(0x3fffffff)) <=
std::exp(-(delta / 2) / temp))) {
if (delta < 0 || (temp > 1e-6 && (ctx->rng() / float(0x3fffffff)) <=
std::exp(-delta / temp))) {
n_accept++;
if (delta < 2)
improved = true;

13
ice40/bitstream.cc
View File

@ -229,6 +229,16 @@ void write_asc(const Context *ctx, std::ostream &out)
set_config(ti, config.at(iey).at(iex),
"IoCtrl.REN_" + std::to_string(iez), !pullup);
}
if (ctx->args.type == ArchArgs::UP5K) {
if (iez == 0) {
set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_39",
!pullup);
} else if (iez == 1) {
set_config(ti, config.at(iey).at(iex), "IoCtrl.cf_bit_35",
!pullup);
}
}
} else if (cell.second->type == ctx->id("SB_GB")) {
// no cell config bits
} else if (cell.second->type == ctx->id("ICESTORM_RAM")) {
@ -312,7 +322,8 @@ void write_asc(const Context *ctx, std::ostream &out)
ctx->args.type == ArchArgs::HX8K) {
setColBufCtrl = (y == 8 || y == 9 || y == 24 || y == 25);
} else if (ctx->args.type == ArchArgs::UP5K) {
if (tile == TILE_LOGIC) {
if (tile == TILE_LOGIC || tile == TILE_RAMB ||
tile == TILE_RAMT) {
setColBufCtrl = (y == 4 || y == 5 || y == 14 || y == 15 ||
y == 26 || y == 27);
} else {