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timing: Improve crit path statistics

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2018-11-16 16:24:06 +00:00
parent 94dc54f4fa
commit 72b53016c0
1 changed files with 7 additions and 2 deletions
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9
common/timing.cc
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@ -593,7 +593,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
if (print_path) { if (print_path) {
auto print_path_report = [ctx](ClockPair &clocks, PortRefVector &crit_path) { auto print_path_report = [ctx](ClockPair &clocks, PortRefVector &crit_path) {
delay_t total = 0; delay_t total = 0, logic_total = 0, route_total = 0;
auto &front = crit_path.front(); auto &front = crit_path.front();
auto &front_port = front->cell->ports.at(front->port); auto &front_port = front->cell->ports.at(front->port);
auto &front_driver = front_port.net->driver; auto &front_driver = front_port.net->driver;
@ -609,6 +609,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
clockInfo.edge == clocks.start.edge) { clockInfo.edge == clocks.start.edge) {
last_port = clockInfo.clock_port; last_port = clockInfo.clock_port;
total += clockInfo.clockToQ.maxDelay(); total += clockInfo.clockToQ.maxDelay();
logic_total += clockInfo.clockToQ.maxDelay();
break; break;
} }
} }
@ -625,14 +626,16 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
if (last_port == driver.port) { if (last_port == driver.port) {
// Case where we start with a STARTPOINT etc // Case where we start with a STARTPOINT etc
comb_delay = ctx->getDelayFromNS(0); comb_delay = ctx->getDelayFromNS(0);
} else if (total == 0) { } else {
ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay); ctx->getCellDelay(sink_cell, last_port, driver.port, comb_delay);
} }
total += comb_delay.maxDelay(); total += comb_delay.maxDelay();
logic_total += comb_delay.maxDelay();
log_info("%4.1f %4.1f Source %s.%s\n", ctx->getDelayNS(comb_delay.maxDelay()), ctx->getDelayNS(total), log_info("%4.1f %4.1f Source %s.%s\n", ctx->getDelayNS(comb_delay.maxDelay()), ctx->getDelayNS(total),
driver_cell->name.c_str(ctx), driver.port.c_str(ctx)); driver_cell->name.c_str(ctx), driver.port.c_str(ctx));
auto net_delay = ctx->getNetinfoRouteDelay(net, *sink); auto net_delay = ctx->getNetinfoRouteDelay(net, *sink);
total += net_delay; total += net_delay;
route_total += net_delay;
auto driver_loc = ctx->getBelLocation(driver_cell->bel); auto driver_loc = ctx->getBelLocation(driver_cell->bel);
auto sink_loc = ctx->getBelLocation(sink_cell->bel); auto sink_loc = ctx->getBelLocation(sink_cell->bel);
log_info("%4.1f %4.1f Net %s budget %f ns (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(net_delay), log_info("%4.1f %4.1f Net %s budget %f ns (%d,%d) -> (%d,%d)\n", ctx->getDelayNS(net_delay),
@ -666,9 +669,11 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0); auto sinkClockInfo = ctx->getPortClockingInfo(crit_path.back()->cell, crit_path.back()->port, 0);
delay_t setup = sinkClockInfo.setup.maxDelay(); delay_t setup = sinkClockInfo.setup.maxDelay();
total += setup; total += setup;
logic_total += setup;
log_info("%4.1f %4.1f Setup %s.%s\n", ctx->getDelayNS(setup), ctx->getDelayNS(total), log_info("%4.1f %4.1f Setup %s.%s\n", ctx->getDelayNS(setup), ctx->getDelayNS(total),
crit_path.back()->cell->name.c_str(ctx), crit_path.back()->port.c_str(ctx)); crit_path.back()->cell->name.c_str(ctx), crit_path.back()->port.c_str(ctx));
} }
log_info("%.1f ns logic, %.1f ns routing\n", ctx->getDelayNS(logic_total), ctx->getDelayNS(route_total));
}; };
for (auto &clock : clock_reports) { for (auto &clock : clock_reports) {