Adding basic placement constraints

Specify the attribute (* LOC="bel_name" *) on any cell to constrain its
placement to that bel.

Signed-off-by: David Shah <davey1576@gmail.com>

common/place.cc

@@ -38,8 +38,38 @@ void place_design(Design *design)
     std::set<IdString>::iterator not_found, element;
     std::set<BelType> used_bels;
 
+    // Initial constraints placer
     for (auto cell_entry : design->cells) {
         CellInfo *cell = cell_entry.second;
+        auto loc = cell->attrs.find("LOC");
+        if (loc != cell->attrs.end()) {
+            std::string loc_name = loc->second;
+            BelId bel = design->chip.getBelByName(IdString(loc_name));
+            if (bel == BelId()) {
+                log_error("No Bel named \'%s\' located for "
+                          "this chip (processing LOC on \'%s\')\n",
+                          loc_name.c_str(), cell->name.c_str());
+            }
+
+            BelType bel_type = design->chip.getBelType(bel);
+            if (bel_type != belTypeFromId(cell->type)) {
+                log_error("Bel \'%s\' of type \'%s\' does not match cell "
+                          "\'%s\' of type \'%s\'",
+                          loc_name.c_str(), belTypeToId(bel_type).c_str(),
+                          cell->name.c_str(), cell->type.c_str());
+            }
+
+            cell->bel = bel;
+            design->chip.bindBel(bel, cell->name);
+        }
+    }
+
+    for (auto cell_entry : design->cells) {
+        CellInfo *cell = cell_entry.second;
+        // Ignore already placed cells
+        if (cell->bel != BelId())
+            continue;
+
         BelType bel_type;
 
         element = types_used.find(cell->type);
@@ -64,17 +94,25 @@ void place_design(Design *design)
         for (auto cell_entry : design->cells) {
             CellInfo *cell = cell_entry.second;
 
+            // Ignore already placed cells
+            if (cell->bel != BelId())
+                continue;
             // Only place one type of Bel at a time
             if (cell->type.compare(bel_type_name) != 0)
                 continue;
 
             while ((bi != blist.end()) &&
-                   (design->chip.getBelType(*bi) != bel_type))
+                   ((design->chip.getBelType(*bi) != bel_type ||
+                     !design->chip.checkBelAvail(*bi))))
                 bi++;
             if (bi == blist.end())
                 log_error("Too many \'%s\' used in design\n",
                           cell->type.c_str());
             cell->bel = *bi++;
+            design->chip.bindBel(cell->bel, cell->name);
+
+            // Back annotate location
+            cell->attrs["LOC"] = design->chip.getBelName(cell->bel);
         }
     }
 }

common/route.cc

@@ -37,7 +37,7 @@ template <> struct greater<QueuedWire>
         return lhs.delay.avgDelay() > rhs.delay.avgDelay();
     }
 };
-}
+} // namespace std
 
 void route_design(Design *design)
 {

ice40/blinky.v

@@ -8,23 +8,97 @@ module blinky (
 );
 	wire clk, led1, led2, led3, led4, led5;
 	
+	(* LOC="0_3_lc0" *)	
 	SB_IO #(
 		.PIN_TYPE(6'b 0110_01),
 		.PULLUP(1'b0),
 		.NEG_TRIGGER(1'b0)
-	) led_iob [4:0] (
+	) led1_iob (
-		.PACKAGE_PIN({led1_pin, led2_pin, led3_pin, led4_pin, led5_pin}),
+		.PACKAGE_PIN(led1_pin),
 		.LATCH_INPUT_VALUE(),
 		.CLOCK_ENABLE(),
 		.INPUT_CLK(),
 		.OUTPUT_CLK(),
 		.OUTPUT_ENABLE(),
-		.D_OUT_0({led1, led2, led3, led4, led5}),
+		.D_OUT_0(led1),
 		.D_OUT_1(),
 		.D_IN_0(),
 		.D_IN_1()
 	);
 	
+	(* LOC="0_3_lc1" *)	
+	SB_IO #(
+		.PIN_TYPE(6'b 0110_01),
+		.PULLUP(1'b0),
+		.NEG_TRIGGER(1'b0)
+	) led2_iob (
+		.PACKAGE_PIN(led2_pin),
+		.LATCH_INPUT_VALUE(),
+		.CLOCK_ENABLE(),
+		.INPUT_CLK(),
+		.OUTPUT_CLK(),
+		.OUTPUT_ENABLE(),
+		.D_OUT_0(led2),
+		.D_OUT_1(),
+		.D_IN_0(),
+		.D_IN_1()
+	);
+
+	(* LOC="5_17_lc1" *)	
+	SB_IO #(
+		.PIN_TYPE(6'b 0110_01),
+		.PULLUP(1'b0),
+		.NEG_TRIGGER(1'b0)
+	) led3_iob (
+		.PACKAGE_PIN(led3_pin),
+		.LATCH_INPUT_VALUE(),
+		.CLOCK_ENABLE(),
+		.INPUT_CLK(),
+		.OUTPUT_CLK(),
+		.OUTPUT_ENABLE(),
+		.D_OUT_0(led3),
+		.D_OUT_1(),
+		.D_IN_0(),
+		.D_IN_1()
+	);
+
+	(* LOC="10_0_lc1" *)	
+	SB_IO #(
+		.PIN_TYPE(6'b 0110_01),
+		.PULLUP(1'b0),
+		.NEG_TRIGGER(1'b0)
+	) led4_iob (
+		.PACKAGE_PIN(led4_pin),
+		.LATCH_INPUT_VALUE(),
+		.CLOCK_ENABLE(),
+		.INPUT_CLK(),
+		.OUTPUT_CLK(),
+		.OUTPUT_ENABLE(),
+		.D_OUT_0(led4),
+		.D_OUT_1(),
+		.D_IN_0(),
+		.D_IN_1()
+	);
+
+	(* LOC="12_17_lc0" *)	
+	SB_IO #(
+		.PIN_TYPE(6'b 0110_01),
+		.PULLUP(1'b0),
+		.NEG_TRIGGER(1'b0)
+	) led5_iob (
+		.PACKAGE_PIN(led5_pin),
+		.LATCH_INPUT_VALUE(),
+		.CLOCK_ENABLE(),
+		.INPUT_CLK(),
+		.OUTPUT_CLK(),
+		.OUTPUT_ENABLE(),
+		.D_OUT_0(led5),
+		.D_OUT_1(),
+		.D_IN_0(),
+		.D_IN_1()
+	);
+
+	(* LOC="0_6_lc0" *)
 	SB_IO #(
 		.PIN_TYPE(6'b 0000_01),
 		.PULLUP(1'b0),

python/dump_design.py

@@ -20,6 +20,6 @@ for cell, cinfo in sorted(design.cells, key=lambda x: x.first):
                 val = "{}'b{}".format(len(val), val)
             print("\t\t{}: {}".format(param, val))
 
-    if not cinfo.bel.nil():
+    if cinfo.bel != -1:
         print("\tBel: {}".format(chip.getBelName(cinfo.bel)))
     print()